Until proper MIPS cache management is available it is necessary to disable data and instruction caches, otherwise code placed in memory stays in data cache and is not available for instruction fetched. BRANCH=none BUG=chrome-os-partner:31438,chrome-os-partner:34127 TEST=coreboot loading rombase and rambase now succeeds. Change-Id: I4147e1325edc0b9bb951cd7ce18d5f104f3eaec0 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 93d5bfa1d01fbbabbabef33a22287ceeea28b15b Original-Change-Id: Ib195ed6e5f08ccaa6bbe3325c2199171bfb63b88 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232191 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9569 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
59 lines
1.5 KiB
ArmAsm
59 lines
1.5 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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.set noreorder /* Prevent assembler from "optimizing" this code. */
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.section ".text._start", "ax", %progbits
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.globl _start
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_start:
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/* Set the stack pointer */
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la $sp, _estack
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/*
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* Initialise the stack to a known value, used later to check for
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* overflow.
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*/
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la $t0, _stack
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addi $t1, $sp, -4
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li $t2, 0xdeadbeef
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1: sw $t2, 0($t0)
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bne $t0, $t1, 1b
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addi $t0, $t0, 4
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/*
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* Disable caches for now, proper cache management is coming soon.
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* http://crosbug.com/p/34127
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*/
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mfc0 $t0, $16
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li $t1, -8
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and $t0, $t0, $t1
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ori $t0, $t0, 2
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mtc0 $t0, $16
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/* Run main */
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b main
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/*
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* Should never return from main. Make sure there is no branch in the
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* branch delay slot.
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*/
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2: nop
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b 2b
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nop /* Make sure there is no branch after this either. */
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