d44a03622e
Define the default value under northbridge. The list of boards this patchset touches will change to use SB_HT_CHAIN_ON_BUS0 with follow-up patch. Based on code analysis, these boards already scan system bus as the first (active) HT chain, so it is placed as bus 0 even when this option was not explicitly selected. Change-Id: I5a00d6372cb89151940aeee517ea613398825c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8353 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
58 lines
871 B
Plaintext
58 lines
871 B
Plaintext
if BOARD_TYAN_S4882
|
|
|
|
config BOARD_SPECIFIC_OPTIONS # dummy
|
|
def_bool y
|
|
select CPU_AMD_SOCKET_940
|
|
select NORTHBRIDGE_AMD_AMDK8
|
|
select SOUTHBRIDGE_AMD_AMD8111
|
|
select SOUTHBRIDGE_AMD_AMD8131
|
|
select SUPERIO_WINBOND_W83627HF
|
|
select HAVE_OPTION_TABLE
|
|
select HAVE_PIRQ_TABLE
|
|
select HAVE_MP_TABLE
|
|
select BOARD_ROMSIZE_KB_512
|
|
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
|
select QRANK_DIMM_SUPPORT
|
|
|
|
config MAINBOARD_DIR
|
|
string
|
|
default tyan/s4882
|
|
|
|
config DCACHE_RAM_BASE
|
|
hex
|
|
default 0xcf000
|
|
|
|
config DCACHE_RAM_SIZE
|
|
hex
|
|
default 0x01000
|
|
|
|
config APIC_ID_OFFSET
|
|
hex
|
|
default 0x10
|
|
|
|
config MAINBOARD_PART_NUMBER
|
|
string
|
|
default "S4882"
|
|
|
|
config MAX_CPUS
|
|
int
|
|
default 8
|
|
|
|
config MAX_PHYSICAL_CPUS
|
|
int
|
|
default 4
|
|
|
|
config HT_CHAIN_END_UNITID_BASE
|
|
hex
|
|
default 0x20
|
|
|
|
config HT_CHAIN_UNITID_BASE
|
|
hex
|
|
default 0x1
|
|
|
|
config IRQ_SLOT_COUNT
|
|
int
|
|
default 22
|
|
|
|
endif # BOARD_TYAN_S4882
|