119ace0908
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
324 lines
11 KiB
Plaintext
324 lines
11 KiB
Plaintext
chip soc/intel/cannonlake
|
|
# Lock Down
|
|
register "common_soc_config" = "{
|
|
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
|
}"
|
|
|
|
# Send an extra VR mailbox command for the PS4 exit issue
|
|
register "SendVrMbxCmd" = "2"
|
|
|
|
# ACPI (soc/intel/cannonlake/acpi.c)
|
|
# Disable s0ix
|
|
register "s0ix_enable" = "0"
|
|
|
|
# PM Timer Enabled
|
|
register "PmTimerDisabled" = "0"
|
|
|
|
# Disable DPTF
|
|
register "dptf_enable" = "0"
|
|
|
|
# CPU (soc/intel/cannonlake/cpu.c)
|
|
# Power limit
|
|
register "power_limits_config" = "{
|
|
.tdp_pl1_override = 25,
|
|
.tdp_pl2_override = 28,
|
|
}"
|
|
|
|
# Enable "Intel Speed Shift Technology"
|
|
register "speed_shift_enable" = "1"
|
|
|
|
# Enable Enhanced Intel SpeedStep
|
|
register "eist_enable" = "1"
|
|
|
|
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
|
|
register "SaGv" = "SaGv_Enabled"
|
|
|
|
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
|
|
# Serial I/O
|
|
register "SerialIoDevMode" = "{
|
|
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
|
}"
|
|
|
|
# SATA
|
|
register "SataMode" = "Sata_AHCI"
|
|
register "SataSalpSupport" = "0"
|
|
register "SataPortsEnable[0]" = "1" # 2.5"
|
|
register "SataPortsEnable[2]" = "1" # m.2
|
|
register "SataPortsDevSlp[0]" = "0"
|
|
register "SataPortsDevSlp[2]" = "0"
|
|
|
|
# Audio
|
|
register "PchHdaDspEnable" = "0"
|
|
register "PchHdaAudioLinkHda" = "1"
|
|
register "PchHdaAudioLinkDmic0" = "0"
|
|
register "PchHdaAudioLinkDmic1" = "0"
|
|
register "PchHdaAudioLinkSsp0" = "0"
|
|
register "PchHdaAudioLinkSsp1" = "0"
|
|
register "PchHdaAudioLinkSsp2" = "0"
|
|
register "PchHdaAudioLinkSndw1" = "0"
|
|
register "PchHdaAudioLinkSndw2" = "0"
|
|
register "PchHdaAudioLinkSndw3" = "0"
|
|
register "PchHdaAudioLinkSndw4" = "0"
|
|
|
|
# USB
|
|
register "SsicPortEnable" = "0"
|
|
|
|
# USB2
|
|
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper
|
|
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower
|
|
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper
|
|
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower
|
|
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper
|
|
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear
|
|
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth
|
|
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC
|
|
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
|
|
register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower
|
|
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC
|
|
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC
|
|
register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC
|
|
register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC
|
|
register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC
|
|
register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC
|
|
|
|
# USB3
|
|
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper
|
|
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower
|
|
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # NC
|
|
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear
|
|
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
|
|
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
|
|
register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC
|
|
register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC
|
|
register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC
|
|
register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC
|
|
|
|
# All SRCCLKREQ pins mapped directly
|
|
register "PcieClkSrcClkReq[0]" = "0"
|
|
register "PcieClkSrcClkReq[1]" = "1"
|
|
register "PcieClkSrcClkReq[2]" = "2"
|
|
register "PcieClkSrcClkReq[3]" = "3"
|
|
register "PcieClkSrcClkReq[4]" = "4"
|
|
register "PcieClkSrcClkReq[5]" = "5"
|
|
|
|
# Set all SRCCLKREQ pins as free-use
|
|
register "PcieClkSrcUsage[0]" = "0x80"
|
|
register "PcieClkSrcUsage[1]" = "0x80"
|
|
register "PcieClkSrcUsage[2]" = "0x80"
|
|
register "PcieClkSrcUsage[3]" = "0x80"
|
|
register "PcieClkSrcUsage[4]" = "0x80"
|
|
register "PcieClkSrcUsage[5]" = "0x80"
|
|
|
|
# PCI Express Root Port #8 x1, Clock 2 (WLAN)
|
|
register "PcieRpEnable[7]" = "1"
|
|
register "PcieRpLtrEnable[7]" = "1"
|
|
|
|
# PCI Express Root Port #10 x1, Clock 3 (LAN)
|
|
register "PcieRpEnable[9]" = "1"
|
|
register "PcieRpLtrEnable[9]" = "0"
|
|
|
|
# PCI Express Root port #13 x4, Clock 1 (NVMe)
|
|
register "PcieRpEnable[12]" = "1"
|
|
register "PcieRpLtrEnable[12]" = "1"
|
|
|
|
# Misc
|
|
register "AcousticNoiseMitigation" = "1"
|
|
register "satapwroptimize" = "1"
|
|
|
|
# Power
|
|
register "PchPmSlpS3MinAssert" = "3" # 50ms
|
|
register "PchPmSlpS4MinAssert" = "1" # 1s
|
|
register "PchPmSlpSusMinAssert" = "2" # 500ms
|
|
register "PchPmSlpAMinAssert" = "4" # 2s
|
|
|
|
# Thermal
|
|
register "tcc_offset" = "12"
|
|
|
|
# Serial IRQ Mode
|
|
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
|
|
|
# PMC (soc/intel/cannonlake/pmc.c)
|
|
# Disable deep Sx states
|
|
register "deep_sx_config" = "0"
|
|
|
|
# PM Util (soc/intel/cannonlake/pmutil.c)
|
|
# GPE configuration
|
|
# Note that GPE events called out in ASL code rely on this
|
|
# route. i.e. If this route changes then the affected GPE
|
|
# offset bits also need to be changed.
|
|
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
|
|
register "gpe0_dw0" = "PMC_GPP_C"
|
|
register "gpe0_dw1" = "PMC_GPP_D"
|
|
register "gpe0_dw2" = "PMC_GPP_E"
|
|
|
|
# Actual device tree
|
|
device cpu_cluster 0 on
|
|
device lapic 0 on end
|
|
end
|
|
|
|
device domain 0 on
|
|
device pci 00.0 on end # Host Bridge
|
|
device pci 02.0 on end # Integrated Graphics Device
|
|
device pci 04.0 on # SA Thermal device
|
|
register "Device4Enable" = "1"
|
|
end
|
|
device pci 12.0 on end # Thermal Subsystem
|
|
device pci 13.0 off end # Integrated Sensor Hub
|
|
device pci 14.0 on # USB xHCI
|
|
chip drivers/usb/acpi
|
|
device usb 0.0 on
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB2 Type-A Front Left Upper""
|
|
register "type" = "UPC_TYPE_A"
|
|
register "group" = "ACPI_PLD_GROUP(0, 0)"
|
|
device usb 2.0 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB2 Type-A Front Left Lower""
|
|
register "type" = "UPC_TYPE_A"
|
|
register "group" = "ACPI_PLD_GROUP(0, 1)"
|
|
device usb 2.1 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB2 Type-A Rear Upper""
|
|
register "type" = "UPC_TYPE_A"
|
|
register "group" = "ACPI_PLD_GROUP(1, 0)"
|
|
device usb 2.2 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB2 Type-A Front Right Lower""
|
|
register "type" = "UPC_TYPE_A"
|
|
register "group" = "ACPI_PLD_GROUP(0, 2)"
|
|
device usb 2.3 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB2 Type-A Front Right Upper""
|
|
register "type" = "UPC_TYPE_A"
|
|
register "group" = "ACPI_PLD_GROUP(0, 3)"
|
|
device usb 2.4 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB2 Type-C Port Rear""
|
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
|
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
|
device usb 2.5 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
device usb 2.6 off end
|
|
end
|
|
chip drivers/usb/acpi
|
|
device usb 2.7 off end
|
|
end
|
|
chip drivers/usb/acpi
|
|
device usb 2.8 off end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB2 Type-A Rear Lower""
|
|
register "type" = "UPC_TYPE_A"
|
|
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
|
device usb 2.9 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB3 Type-A Front Left Upper""
|
|
register "type" = "UPC_TYPE_USB3_A"
|
|
register "group" = "ACPI_PLD_GROUP(0, 0)"
|
|
device usb 3.0 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB3 Type-A Front Left Lower""
|
|
register "type" = "UPC_TYPE_USB3_A"
|
|
register "group" = "ACPI_PLD_GROUP(0, 1)"
|
|
device usb 3.1 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
device usb 3.2 off end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB3 Type-C Rear""
|
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
|
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
|
device usb 3.3 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB3 Type-A Rear Lower""
|
|
register "type" = "UPC_TYPE_USB3_A"
|
|
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
|
device usb 3.4 on end
|
|
end
|
|
chip drivers/usb/acpi
|
|
register "desc" = ""USB3 Type-A Rear Upper""
|
|
register "type" = "UPC_TYPE_USB3_A"
|
|
register "group" = "ACPI_PLD_GROUP(1, 0)"
|
|
device usb 3.5 on end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
device pci 14.1 off end # USB xDCI (OTG)
|
|
device pci 15.0 off end # I2C #0
|
|
device pci 15.1 off end # I2C #1
|
|
device pci 15.2 off end # I2C #2
|
|
device pci 15.3 off end # I2C #3
|
|
device pci 16.0 off # Management Engine Interface 1
|
|
# HECI must be enabled w/HAP disable else S3 issues
|
|
register "HeciEnabled" = "1"
|
|
end
|
|
device pci 16.1 off end # Management Engine Interface 2
|
|
device pci 16.2 off end # Management Engine IDE-R
|
|
device pci 16.3 off end # Management Engine KT Redirection
|
|
device pci 16.4 off # Management Engine Interface 3
|
|
register "Heci3Enabled" = "0"
|
|
end
|
|
device pci 16.5 off end # Management Engine Interface 4
|
|
device pci 17.0 on end # SATA
|
|
device pci 19.0 off end # I2C #4
|
|
device pci 19.1 off end # I2C #5
|
|
device pci 19.2 off end # UART #2
|
|
device pci 1a.0 off end # eMMC
|
|
device pci 1c.0 off end # PCI Express Port 1
|
|
device pci 1c.1 off end # PCI Express Port 2
|
|
device pci 1c.2 off end # PCI Express Port 3
|
|
device pci 1c.3 off end # PCI Express Port 4
|
|
device pci 1c.4 off end # PCI Express Port 5
|
|
device pci 1c.5 off end # PCI Express Port 6
|
|
device pci 1c.6 off end # PCI Express Port 7
|
|
device pci 1c.7 on # PCI Express Port 8 (WLAN)
|
|
register "PcieRpSlotImplemented[7]" = "1"
|
|
end
|
|
device pci 1d.0 off end # PCI Express Port 9
|
|
device pci 1d.1 on # PCI Express Port 10 (LAN)
|
|
register "PcieRpSlotImplemented[9]" = "1"
|
|
end
|
|
device pci 1d.2 off end # PCI Express Port 11
|
|
device pci 1d.3 off end # PCI Express Port 12
|
|
device pci 1d.4 on # PCI Express Port 13 (NVMe)
|
|
register "PcieRpSlotImplemented[12]" = "1"
|
|
end
|
|
device pci 1d.5 off end # PCI Express Port 14
|
|
device pci 1d.6 off end # PCI Express Port 15
|
|
device pci 1d.7 off end # PCI Express Port 16
|
|
device pci 1e.0 off end # UART #0
|
|
device pci 1e.1 off end # UART #1
|
|
device pci 1e.2 off end # GSPI #0
|
|
device pci 1e.3 off end # GSPI #1
|
|
device pci 1f.0 on end # LPC Bridge
|
|
device pci 1f.1 off end # P2SB
|
|
device pci 1f.2 off end # Power Management Controller
|
|
device pci 1f.3 on end # Intel HDA
|
|
device pci 1f.4 on end # SMBus
|
|
device pci 1f.5 on end # PCH SPI
|
|
device pci 1f.6 off end # GbE
|
|
end
|
|
end
|