1201fb9a91
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/iomap.h>
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#include <amdblocks/mca.h>
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#include <console/console.h>
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#include <cpu/amd/microcode.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/mtrr.h>
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#include <device/device.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
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"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
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/* MP and SMM loading initialization */
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void mp_init_cpus(struct bus *cpu_bus)
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{
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extern const struct mp_ops amd_mp_ops_with_smm;
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if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"mp_init_with_smm failed. Halting.\n");
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/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
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mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
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FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
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/* SMMINFO only needs to be set up when booting from S5 */
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if (!acpi_is_wakeup_s3())
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apm_control(APM_CNT_SMMINFO);
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}
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static void zen_2_3_init(struct device *dev)
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{
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check_mca();
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set_cstate_io_addr();
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amd_update_microcode_from_cbfs();
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}
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static struct device_operations cpu_dev_ops = {
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.init = zen_2_3_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, CEZANNE_A0_CPUID},
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{ 0, 0 },
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};
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static const struct cpu_driver zen_2_3 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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