129ed0a264
This cleans up the postcar frame setup, which now gets used instead of just going with TempRamExit MTRR's. Note that ramstage CPU init sets up different final MTRRs anyway. TESTED on ocp/deltalake and ocp/tiogapass. Change-Id: I756c2d479fef859a460696300422f08013a300f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
112 lines
2.6 KiB
Plaintext
112 lines
2.6 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-or-later
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source "src/soc/intel/xeon_sp/skx/Kconfig"
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source "src/soc/intel/xeon_sp/cpx/Kconfig"
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config XEON_SP_COMMON_BASE
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bool
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config SOC_INTEL_SKYLAKE_SP
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bool
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select XEON_SP_COMMON_BASE
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select PLATFORM_USES_FSP2_0
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help
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Intel Skylake-SP support
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config SOC_INTEL_COOPERLAKE_SP
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bool
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select XEON_SP_COMMON_BASE
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select PLATFORM_USES_FSP2_2
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select CACHE_MRC_SETTINGS
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help
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Intel Cooperlake-SP support
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if XEON_SP_COMMON_BASE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_ALL_STAGES_X86_32
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CPU_INTEL_COMMON
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_RESET
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select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
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select FSP_T_XIP
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select FSP_M_XIP
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select POSTCAR_STAGE
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select IOAPIC
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select PARALLEL_MP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_DMI
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select SOC_INTEL_COMMON_BLOCK_TIMER
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select SOC_INTEL_COMMON_BLOCK_LPC
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select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI
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select SOC_INTEL_COMMON_BLOCK_RTC
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select SOC_INTEL_COMMON_BLOCK_SPI
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
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select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_P2SB
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select SOC_INTEL_COMMON_BLOCK_PMC
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select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_TCO
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select TSC_MONOTONIC_TIMER
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select UDELAY_TSC
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select FSP_CAR
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select CPU_INTEL_COMMON_SMM
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select SMM_TSEG
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select HAVE_SMI_HANDLER
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select X86_SMM_LOADER_VERSION2
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select REG_SCRIPT
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select NO_FSP_TEMP_RAM_EXIT
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select INTEL_CAR_NEM # For postcar only now
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config MAINBOARD_USES_FSP2_0
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bool
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default y
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config USE_FSP2_0_DRIVER
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def_bool y
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depends on MAINBOARD_USES_FSP2_0
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select PLATFORM_USES_FSP2_0
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select UDK_202005_BINDING
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select POSTCAR_STAGE
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config MAX_SOCKET
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int
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default 2
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# For 2S config, the number of cpus could be as high as
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# 2 threads * 20 cores * 2 sockets
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config MAX_CPUS
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int
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default 80
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config PCR_BASE_ADDRESS
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hex
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x10000
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config MMCONF_BASE_ADDRESS
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default 0x80000000
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config HEAP_SIZE
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hex
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default 0x80000
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endif ## SOC_INTEL_XEON_SP
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