12a448224f
This makes sure that the resource allocator won't use this address range for anything else. In the systems I looked at, this was between the end of the above 4GB memory and the beginning of the above 4GB PCI BAR MMIO region, but better reserve it here so nothing else will get allocated there if this expectation isn't met. TEST=Reserved region is printed in the console logs: update_constraints: PCI: 00:00.0 09 base fd00000000 limit fdffffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
222 lines
8.4 KiB
C
222 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/alib.h>
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#include <amdblocks/data_fabric.h>
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#include <amdblocks/memmap.h>
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#include <amdblocks/ioapic.h>
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#include <amdblocks/iomap.h>
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#include <arch/ioapic.h>
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#include <arch/vga.h>
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#include <assert.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/util.h>
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#include <stdint.h>
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#include <soc/iomap.h>
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#include "chip.h"
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#define DPTC_TOTAL_UPDATE_PARAMS 4
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struct dptc_input {
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uint16_t size;
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struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS];
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} __packed;
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#define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \
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{ \
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.size = sizeof(struct dptc_input), \
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.params = { \
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{ \
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.id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \
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.value = _thermctllmit, \
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}, \
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{ \
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.id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \
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.value = _sustained, \
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}, \
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{ \
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.id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \
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.value = _fast, \
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}, \
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{ \
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.id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \
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.value = _slow, \
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}, \
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}, \
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}
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/*
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*
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* +--------------------------------+
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* reserved_dram_end +--------------------------------+
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* | |
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* | verstage (if reqd) |
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* | (VERSTAGE_SIZE) |
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* +--------------------------------+ VERSTAGE_ADDR
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* | |
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* | FSP-M |
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* | (FSP_M_SIZE) |
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* +--------------------------------+ FSP_M_ADDR
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* | romstage |
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* | (ROMSTAGE_SIZE) |
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* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
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* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
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* | bootblock |
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* | (C_ENV_BOOTBLOCK_SIZE) |
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* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
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* | Unused hole |
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* | (86KiB) |
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* +--------------------------------+
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* | FMAP cache (FMAP_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
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* | Early Timestamp region (512B) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
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* | Preram CBMEM console |
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* | (PRERAM_CBMEM_CONSOLE_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
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* | PSP shared (vboot workbuf) |
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* | (PSP_SHAREDMEM_SIZE) |
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* +--------------------------------+ PSP_SHAREDMEM_BASE
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* | APOB (64KiB) |
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* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
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* | Early BSP stack |
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* | (EARLYRAM_BSP_STACK_SIZE) |
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* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
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* | DRAM |
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* +--------------------------------+ 0x100000
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* | Option ROM |
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* +--------------------------------+ 0xc0000
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* | Legacy VGA |
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* +--------------------------------+ 0xa0000
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* | DRAM |
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* +--------------------------------+ 0x0
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*/
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static void read_resources(struct device *dev)
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{
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uint32_t mem_usable = (uintptr_t)cbmem_top();
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unsigned int idx = 0;
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const struct hob_header *hob_iterator;
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const struct hob_resource *res;
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struct resource *gnb_apic;
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uintptr_t early_reserved_dram_start, early_reserved_dram_end;
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const struct memmap_early_dram *e = memmap_get_early_dram_usage();
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early_reserved_dram_start = e->base;
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early_reserved_dram_end = e->base + e->size;
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/* The root complex has no PCI BARs implemented, so there's no need to call
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pci_dev_read_resources for it */
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fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
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/* 0x0 - 0x9ffff */
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ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
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/* 0xa0000 - 0xbffff: legacy VGA */
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mmio_resource_kb(dev, idx++, VGA_MMIO_BASE / KiB, VGA_MMIO_SIZE / KiB);
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/* 0xc0000 - 0xfffff: Option ROM */
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reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
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/* 1MB - bottom of DRAM reserved for early coreboot usage */
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ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
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(early_reserved_dram_start - (1 * MiB)) / KiB);
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/* DRAM reserved for early coreboot usage */
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reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB,
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(early_reserved_dram_end - early_reserved_dram_start) / KiB);
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/* top of DRAM consumed early - low top usable RAM
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* cbmem_top() accounts for low UMA and TSEG if they are used. */
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ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB,
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(mem_usable - early_reserved_dram_end) / KiB);
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mmconf_resource(dev, idx++);
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/* GNB IOAPIC resource */
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gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX);
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gnb_apic->base = GNB_IO_APIC_ADDR;
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gnb_apic->size = 0x00001000;
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gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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/* Reserve fixed IOMMU MMIO region */
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mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
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if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) {
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printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__);
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return;
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}
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while (fsp_hob_iterator_get_next_resource(&hob_iterator, &res) == CB_SUCCESS) {
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if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable)
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continue; /* 0 through low usable was set above */
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if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO)
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continue; /* Done separately */
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if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
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ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
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else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
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reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
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else
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printk(BIOS_ERR, "failed to set resources for type %d\n",
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res->type);
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}
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}
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static void root_complex_init(struct device *dev)
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{
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register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
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}
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static void acipgen_dptci(void)
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{
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const struct soc_amd_picasso_config *config = config_of_soc();
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/* Normal mode DPTC values. */
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struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
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config->sustained_power_limit_mW,
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config->fast_ppt_limit_mW,
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config->slow_ppt_limit_mW);
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acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
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/* Tablet Mode */
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struct dptc_input tablet_mode_input = DPTC_INPUTS(
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config->thermctl_limit_tablet_mode_degreeC,
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config->sustained_power_limit_tablet_mode_mW,
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config->fast_ppt_limit_tablet_mode_mW,
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config->slow_ppt_limit_tablet_mode_mW);
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acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_mode_input,
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sizeof(tablet_mode_input));
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}
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static void root_complex_fill_ssdt(const struct device *device)
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{
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if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
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acipgen_dptci();
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}
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static const char *gnb_acpi_name(const struct device *dev)
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{
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return "GNB";
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}
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struct device_operations picasso_root_complex_operations = {
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.read_resources = read_resources,
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.set_resources = noop_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = root_complex_init,
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.acpi_name = gnb_acpi_name,
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.acpi_fill_ssdt = root_complex_fill_ssdt,
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};
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