12aba82e55
3 (with one of them way too much assembler code). On the way, I had to make some changes to the way the code is built, which is an effort I want to expand over time. Right now, large portions of the in-ROM part of coreboot is compiled as a single file, with lots of .c files including other .c files. That has its justification for pre-raminit code, but it also affects lots of post-raminit code (memcpy doesn't really make sense before raminit, or at least CAR) The coreboot_apc code (AMD boards) gained some .c includes because I don't know that part of the code enough to really rework it and only have limited possibilities to test it. The includes should give an identical situation for this part of the code. This change was posted as set of 6 patches to the list, but they were mostly split for review purposes, hence commit them all at once. They can still be backed up using the patch files, if necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
372 lines
10 KiB
C
372 lines
10 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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// __ROMCC__ means: use "unsigned" for device, not a struct.
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#define __ROMCC__
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include "superio/winbond/w83627thg/w83627thg.h"
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include <cpu/x86/bist.h>
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#include "ram/ramtest.c"
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#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
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#include "reset.c"
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#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
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#include "northbridge/intel/i945/udelay.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
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#include "northbridge/intel/i945/ich7.h"
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static void setup_ich7_gpios(void)
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{
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/* TODO: This is highly board specific and should be moved */
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printk_debug(" GPIOS...");
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/* General Registers */
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outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
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outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
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outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
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/* Output Control Registers */
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outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
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/* Input Control Registers */
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outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
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outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
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outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
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outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
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}
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#include "northbridge/intel/i945/early_init.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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/* Usually system firmware turns off system memory clock signals to
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* unused SO-DIMM slots to reduce EMI and power consumption.
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* However, the Kontron 986LCD-M does not like unused clock signals to
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* be disabled. If other similar mainboard occur, it would make sense
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* to make this an entry in the sysinfo structure, and pre-initialize that
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* structure in the mainboard's auto.c main() function. For now a
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* #define will do.
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*/
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#define OVERRIDE_CLOCK_DISABLE 1
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#define CHANNEL_XOR_RANDOMIZATION 1
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#include "northbridge/intel/i945/raminit.h"
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#include "northbridge/intel/i945/raminit.c"
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#include "northbridge/intel/i945/reset_test.c"
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#include "northbridge/intel/i945/errata.c"
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#include "debug.c"
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static void ich7_enable_lpc(void)
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{
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// Enable Serial IRQ
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
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// Set COM1/COM2 decode range
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
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// Enable COM1/COM2/KBD/SuperIO1+2
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pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
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// Enable HWM at 0xa00
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
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// COM3 decode
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
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// COM4 decode
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
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// io 0x300 decode
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
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}
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/* This box has two superios, so enabling serial becomes slightly excessive.
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* We disable a lot of stuff to make sure that there are no conflicts between
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* the two. Also set up the GPIOs from the beginning. This is the "no schematic
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* but safe anyways" method.
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*/
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static void early_superio_config_w83627thg(void)
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{
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device_t dev;
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dev=PNP_DEV(0x2e, W83627THG_SP1);
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
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pnp_set_enable(dev, 1);
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dev=PNP_DEV(0x2e, W83627THG_SP2);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
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// pnp_write_config(dev, 0xf1, 4); // IRMODE0
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pnp_set_enable(dev, 1);
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dev=PNP_DEV(0x2e, W83627THG_KBC);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
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pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
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// pnp_write_config(dev, 0xf0, 0x82);
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pnp_set_enable(dev, 1);
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dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
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pnp_set_enable(dev, 1);
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dev=PNP_DEV(0x2e, W83627THG_GPIO2);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 1); // Just enable it
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dev=PNP_DEV(0x2e, W83627THG_GPIO3);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
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pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
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pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
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dev=PNP_DEV(0x2e, W83627THG_FDC);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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dev=PNP_DEV(0x2e, W83627THG_PP);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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/* Enable HWM */
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dev=PNP_DEV(0x2e, W83627THG_HWM);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
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pnp_set_enable(dev, 1);
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pnp_exit_ext_func_mode(dev);
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dev=PNP_DEV(0x4e, W83627THG_SP1);
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
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pnp_set_enable(dev, 1);
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dev=PNP_DEV(0x4e, W83627THG_SP2);
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pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
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pnp_set_enable(dev, 1);
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dev=PNP_DEV(0x4e, W83627THG_FDC);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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dev=PNP_DEV(0x4e, W83627THG_PP);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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dev=PNP_DEV(0x4e, W83627THG_KBC);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
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pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
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pnp_exit_ext_func_mode(dev);
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}
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static void rcba_config(void)
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{
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/* Set up virtual channel 0 */
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//RCBA32(0x0014) = 0x80000001;
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//RCBA32(0x001c) = 0x03128010;
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/* Device 1f interrupt pin register */
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RCBA32(0x3100) = 0x00042210;
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/* Device 1d interrupt pin register */
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RCBA32(0x310c) = 0x00214321;
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/* dev irq route register */
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RCBA16(0x3140) = 0x0132;
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RCBA16(0x3142) = 0x3241;
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RCBA16(0x3144) = 0x0237;
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RCBA16(0x3146) = 0x3210;
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RCBA16(0x3148) = 0x3210;
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/* Enable IOAPIC */
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RCBA8(0x31ff) = 0x03;
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/* Enable upper 128bytes of CMOS */
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RCBA32(0x3400) = (1 << 2);
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/* Disable unused devices */
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RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
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RCBA32(0x3418) |= (1 << 0); // Required.
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/* Enable PCIe Root Port Clock Gate */
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// RCBA32(0x341c) = 0x00000001;
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}
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static void early_ich7_init(void)
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{
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uint8_t reg8;
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uint32_t reg32;
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// program secondary mlt XXX byte?
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pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
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// reset rtc power status
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
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reg8 &= ~(1 << 2);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
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// usb transient disconnect
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
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reg8 |= (3 << 0);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
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reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
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reg32 |= (1 << 29) | (1 << 17);
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pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
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reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
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reg32 |= (1 << 31) | (1 << 27);
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pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
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RCBA32(0x0088) = 0x0011d000;
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RCBA16(0x01fc) = 0x060f;
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RCBA32(0x01f4) = 0x86000040;
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RCBA32(0x0214) = 0x10030549;
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RCBA32(0x0218) = 0x00020504;
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RCBA8(0x0220) = 0xc5;
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reg32 = RCBA32(0x3410);
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reg32 |= (1 << 6);
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RCBA32(0x3410) = reg32;
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reg32 = RCBA32(0x3430);
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reg32 &= ~(3 << 0);
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reg32 |= (1 << 0);
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RCBA32(0x3430) = reg32;
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RCBA32(0x3418) |= (1 << 0);
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RCBA16(0x0200) = 0x2008;
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RCBA8(0x2027) = 0x0d;
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RCBA16(0x3e08) |= (1 << 7);
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RCBA16(0x3e48) |= (1 << 7);
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RCBA32(0x3e0e) |= (1 << 7);
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RCBA32(0x3e4e) |= (1 << 7);
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// next step only on ich7m b0 and later:
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reg32 = RCBA32(0x2034);
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reg32 &= ~(0x0f << 16);
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reg32 |= (5 << 16);
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RCBA32(0x2034) = reg32;
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}
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#if USE_FALLBACK_IMAGE == 1
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#include "southbridge/intel/i82801gx/cmos_failover.c"
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#endif
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void real_main(unsigned long bist)
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{
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int boot_mode = 0;
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if (bist == 0) {
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enable_lapic();
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}
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ich7_enable_lpc();
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early_superio_config_w83627thg();
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/* Set up the console */
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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if (MCHBAR16(SSKPD) == 0xCAFE) {
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printk_debug("soft reset detected.\n");
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boot_mode = 1;
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}
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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*/
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i945_early_initialization();
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/* Enable SPD ROMs and DDR-II DRAM */
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enable_smbus();
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#if DEFAULT_CONSOLE_LOGLEVEL > 8
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dump_spd_registers();
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#endif
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sdram_initialize(boot_mode);
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/* Perform some initialization that must run before stage2 */
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early_ich7_init();
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/* This should probably go away. Until now it is required
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* and mainboard specific
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*/
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rcba_config();
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/* Chipset Errata! */
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fixup_i945_errata();
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/* Initialize the internal PCIe links before we go into stage2 */
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i945_late_initialization();
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#if DEFAULT_CONSOLE_LOGLEVEL > 8
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#if defined(DEBUG_RAM_SETUP)
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sdram_dump_mchbar_registers();
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#endif
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{
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/* This will not work if TSEG is in place! */
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u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
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printk_debug("TOM: 0x%08x\n", tom);
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ram_check(0x00000000, 0x000a0000);
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ram_check(0x00100000, tom);
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}
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#endif
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MCHBAR16(SSKPD) = 0xCAFE;
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}
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#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
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