12b121cdb4
Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
135 lines
4.7 KiB
C
135 lines
4.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
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#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
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#if !defined(__ACPI__)
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#ifndef __ROMCC__
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#include <device/device.h>
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void i82371eb_enable(struct device *dev);
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#endif
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void i82371eb_hard_reset(void);
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void enable_smbus(void);
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void enable_pm(void);
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#if ENV_ROMSTAGE
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int smbus_read_byte(u8 device, u8 address);
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#endif
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#endif
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/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
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* 'reg' variable, otherwise it clears those bits.
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*
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* Examples:
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* reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5));
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* reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR));
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*/
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/* TODO: Move into some global header file? */
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#define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits)))
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#define XBCS 0x4e /* X-Bus chip select register */
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#define GENCFG 0xb0 /* General configuration register */
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#define RC 0xcf9 /* Reset control register */
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/* IDE */
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#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */
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#define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */
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#define UDMACTL 0x48 /* Ultra DMA/33 control register */
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#define UDMATIM 0x4a /* Ultra DMA/33 timing register */
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/* SMBus */
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#define SMBBA 0x90 /* SMBus base address */
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#define SMBUS_IO_BASE 0x0f00
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#define SMBHSTCFG 0xd2 /* SMBus host configuration */
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/* Power management (ACPI) */
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#define PMSTS 0x00 /* Power Management Status */
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#define PMEN 0x02 /* Power Management Resume Enable */
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#define PWRBTN_EN (1<<8)
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#define GBL_EN (1<<5)
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#define PMCNTRL 0x04 /* Power Management Control */
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#define SUS_EN (1<<13) /* S0-S5 trigger */
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#define SUS_TYP_MSK (7<<10)
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#define SUS_TYP_S0 (5<<10)
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#define SUS_TYP_S1 (4<<10)
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#define SUS_TYP_S2 (3<<10)
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//#define SUS_TYP_S2>---(2<<10)
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#define SUS_TYP_S3 (1<<10)
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#define SUS_TYP_S5 (0<<10)
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#define SCI_EN (1<<0)
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#define PMTMR 0x08 /* Power Management Timer */
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#define GPSTS 0x0c /* General Purpose Status */
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#define GPEN 0x0e /* General Purpose Enable */
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#define THRM_EN (1<<0)
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#define PCNTRL 0x10 /* Processor control */
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#define GLBSTS 0x18 /* Global Status */
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#define IRQ_RSM_STS (1<<11)
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#define EXTSMI_STS (1<<10)
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#define GSTBY_STS (1<<8)
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#define GP_STS (1<<7)
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#define BM1_STS (1<<6)
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#define APM_STS (1<<5)
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#define DEV_STS (1<<4)
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#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */
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#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */
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#define DEVSTS 0x1c /* Device Status */
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#define GLBEN 0x20 /* Global Enable */
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#define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */
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#define GSTBY_EN (1<<8)
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#define BM_TRP_EN (1<<1)
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#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */
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#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */
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#define GLBCTL 0x28 /* Global Control */
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#define EOS (1<<16) /* End of SMI */
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#define SMI_EN (1<<0) /* SMI enable */
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#define DEVCTL 0x2c /* Device Control */
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#define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */
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#define GPO0 0x34
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#define GPO1 0x35
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#define GPO2 0x36
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#define GPO3 0x37
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#define PMBA 0x40 /* Power management base address */
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#define DEFAULT_PMBASE 0xe400
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#define PM_IO_BASE DEFAULT_PMBASE
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#define PMREGMISC 0x80 /* Miscellaneous power management */
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/* Bit definitions */
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#define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */
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#define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */
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#define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */
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#define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */
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#define SRST (1 << 1) /* System Reset */
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#define RCPU (1 << 2) /* Reset CPU */
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#define SMB_HST_EN (1 << 0) /* Host Interface Enable */
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#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */
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#define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */
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#define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */
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#define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */
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#define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */
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#define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */
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#define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */
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#define ISA (1 << 0) /* Select ISA */
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#define EIO (0 << 0) /* Select EIO */
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#define PMIOSE (1 << 0) /* PM I/O Space Enable */
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#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
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