12c6a58857
The MADT doesn't populate the IO-APICs yet since we need FSP to configure those. The FADT differs from picasso in the following ways: * The duty_offset is supposed to be 0 * Don't clear x_firmware_ctl_l * Make the extended addresses use MMIO Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* ACPI - create the Fixed ACPI Description Tables (FADT) */
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#include <acpi/acpi.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/acpimmio.h>
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#include <arch/smp/mpspec.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <soc/acpi.h>
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#include <soc/iomap.h>
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#include <types.h>
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#include "chip.h"
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* create all subtables for processors */
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current = acpi_create_madt_lapics(current);
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/* TODO: Add IOAPIC and GNB-IOAPIC */
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current += acpi_create_madt_irqoverride(
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(acpi_madt_irqoverride_t *)current,
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MP_BUS_ISA, 0, 2,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT);
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current += acpi_create_madt_irqoverride(
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(acpi_madt_irqoverride_t *)current,
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MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ,
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MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
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return current;
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}
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/*
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* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
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* in the ACPI 3.0b specification.
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*/
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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const struct soc_amd_common_config *cfg = soc_get_common_config();
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printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
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fadt->sci_int = ACPI_SCI_IRQ;
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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}
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fadt->pstate_cnt = 0;
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fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
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fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
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fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
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fadt->gpe0_blk = ACPI_GPE0_BLK;
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fadt->pm1_evt_len = 4; /* 32 bits */
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fadt->pm1_cnt_len = 2; /* 16 bits */
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fadt->pm_tmr_len = 4; /* 32 bits */
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fadt->gpe0_blk_len = 8; /* 64 bits */
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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fadt->duty_offset = 0; /* Not supported */
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fadt->duty_width = 0; /* Not supported */
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fadt->day_alrm = RTC_DATE_ALARM;
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fadt->mon_alrm = 0;
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fadt->century = RTC_ALT_CENTURY;
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fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */
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fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */
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ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_32BIT_TIMER |
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ACPI_FADT_PCI_EXPRESS_WAKE |
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ACPI_FADT_PLATFORM_CLOCK |
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ACPI_FADT_S4_RTC_VALID |
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ACPI_FADT_REMOTE_POWER_ON;
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fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */
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/*
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* The Cezanne PPR defines the ACPI registers starting at PMx00000500. This translates
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* to 0x300 + 0x500 = 0x800 which is identical to acpimmio_acpi.
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*/
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = (u32)acpimmio_acpi + MMIO_ACPI_PM1_EVT_BLK;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY;
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fadt->x_pm1a_cnt_blk.bit_width = 16;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = (u32)acpimmio_acpi + MMIO_ACPI_PM1_CNT_BLK;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = (u32)acpimmio_acpi + MMIO_ACPI_PM_TMR_BLK;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY;
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fadt->x_gpe0_blk.bit_width = 64;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_gpe0_blk.addrl = (u32)acpimmio_acpi + MMIO_ACPI_GPE0_BLK;
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fadt->x_gpe0_blk.addrh = 0x0;
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}
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