132bbe6be5
Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Test: boot Windows 10 on google/edgar with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright 2013 Google Inc.
|
|
* Copyright (C) 2015 Intel Corp.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include "chip.h"
|
|
#include <arch/io.h>
|
|
#include <console/console.h>
|
|
#include <device/device.h>
|
|
#include <device/pci.h>
|
|
#include <device/pci_ids.h>
|
|
#include <drivers/intel/gma/opregion.h>
|
|
#include <reg_script.h>
|
|
#include <soc/gfx.h>
|
|
#include <soc/nvs.h>
|
|
#include <soc/pci_devs.h>
|
|
#include <soc/ramstage.h>
|
|
|
|
static const struct reg_script gpu_pre_vbios_script[] = {
|
|
/* Make sure GFX is bus master with MMIO access */
|
|
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
|
|
REG_SCRIPT_END
|
|
};
|
|
|
|
static const struct reg_script gfx_post_vbios_script[] = {
|
|
/* Set Lock bits */
|
|
REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK),
|
|
REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK),
|
|
REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK),
|
|
REG_SCRIPT_END
|
|
};
|
|
|
|
static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
|
|
{
|
|
reg_script_run_on_dev(dev, ops);
|
|
}
|
|
|
|
static void gfx_pre_vbios_init(device_t dev)
|
|
{
|
|
printk(BIOS_SPEW, "%s/%s ( %s )\n",
|
|
__FILE__, __func__, dev_name(dev));
|
|
printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
|
|
gfx_run_script(dev, gpu_pre_vbios_script);
|
|
}
|
|
|
|
static void gfx_post_vbios_init(device_t dev)
|
|
{
|
|
printk(BIOS_SPEW, "%s/%s ( %s )\n",
|
|
__FILE__, __func__, dev_name(dev));
|
|
printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
|
|
gfx_run_script(dev, gfx_post_vbios_script);
|
|
}
|
|
|
|
static void gfx_init(device_t dev)
|
|
{
|
|
printk(BIOS_SPEW, "%s/%s ( %s )\n",
|
|
__FILE__, __func__, dev_name(dev));
|
|
|
|
/* Pre VBIOS Init */
|
|
gfx_pre_vbios_init(dev);
|
|
|
|
/* Run VBIOS */
|
|
pci_dev_init(dev);
|
|
|
|
/* Post VBIOS Init */
|
|
gfx_post_vbios_init(dev);
|
|
|
|
intel_gma_restore_opregion();
|
|
}
|
|
|
|
uintptr_t gma_get_gnvs_aslb(const void *gnvs)
|
|
{
|
|
const global_nvs_t *gnvs_ptr = gnvs;
|
|
return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
|
|
}
|
|
|
|
void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
|
|
{
|
|
global_nvs_t *gnvs_ptr = gnvs;
|
|
if (gnvs_ptr)
|
|
gnvs_ptr->aslb = aslb;
|
|
}
|
|
|
|
static struct device_operations gfx_device_ops = {
|
|
.read_resources = pci_dev_read_resources,
|
|
.set_resources = pci_dev_set_resources,
|
|
.enable_resources = pci_dev_enable_resources,
|
|
.init = gfx_init,
|
|
.ops_pci = &soc_pci_ops,
|
|
};
|
|
|
|
static const struct pci_driver gfx_driver __pci_driver = {
|
|
.ops = &gfx_device_ops,
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = GFX_DEVID,
|
|
};
|