sravan/system76-coreboot
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1331815d90a68b7aeb9e2a345f8751b962026e24
system76-coreboot/src
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Jeremy Soller 1331815d90 Disable CPU PCIe clock req messaging 
Change-Id: I7936a770463d150b5310b89a4ab577d8c9aacc98
2020-11-17 20:48:05 -07:00
..
acpi
[TEST] LPIT table test implementation
2020-11-16 19:54:13 -07:00
arch
arch/x86/smbios: Populate SMBIOS type 7 with cache information
2020-10-26 06:54:04 +00:00
commonlib
lib/libpayload: Replace strapping_ids with new board configuration entry
2020-10-30 15:25:28 +00:00
console
console: Override uart base address
2020-11-09 07:46:10 +00:00
cpu
cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers
2020-11-10 06:18:05 +00:00
device
device/pciexp: Allow ASPM on bridge devices
2020-11-17 19:13:14 -07:00
drivers
Merge remote-tracking branch 'upstream/master' into galp5
2020-11-14 19:56:37 -07:00
ec
Merge remote-tracking branch 'upstream/master' into galp5
2020-11-14 19:56:37 -07:00
include
[TEST] LPIT table test implementation
2020-11-16 19:54:13 -07:00
lib
lib/libpayload: Replace strapping_ids with new board configuration entry
2020-10-30 15:25:28 +00:00
mainboard
Disable debug console
2020-11-17 13:53:16 -07:00
northbridge
mrc_cache: Move code for triggering memory training into mrc_cache
2020-11-13 22:57:50 +00:00
security
sec/intel/cbnt: Stitch in ACMs in the coreboot image
2020-11-10 06:17:24 +00:00
soc
Disable CPU PCIe clock req messaging
2020-11-17 20:48:05 -07:00
southbridge
sb/intel/lynxpoint/acpi/pch.asl: Drop unused FD definitions
2020-11-13 13:05:05 +00:00
superio
superio/nuvoton: Factor out equivalent Kconfig option
2020-10-19 07:06:20 +00:00
vendorcode
vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454
2020-11-13 17:56:46 +00:00
Kconfig
[TEST] LPIT table test implementation
2020-11-16 19:54:13 -07:00