1397fd3668
Brox has SSD and UFS storage per different SKU. 1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio settings according to the schematic. 2. Enable UFS, also enable ISH since it is PCI function 0, required for UFS function 7 to be enabled. 3. Set unused SRCCLKREQ signals to NC. 4. Remove unused gpio settings in variant gpio table to prevent unexpected overrides. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
154 lines
3.6 KiB
Plaintext
154 lines
3.6 KiB
Plaintext
config BOARD_GOOGLE_BROX_COMMON
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def_bool n
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_DPTF
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select DRIVERS_INTEL_DPTF_SUPPORTS_TPCH
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_INTEL_USB4_RETIMER
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select DRIVERS_SPI_ACPI
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select DRIVERS_WIFI_GENERIC
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_SKUID
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select ENABLE_TCSS_USB_DETECTION if !CHROMEOS
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select FW_CONFIG
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select FW_CONFIG_SOURCE_CHROMEEC_CBI
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
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select I2C_TPM
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_TPM2
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select PMC_IPC_ACPI_INTERFACE
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select SOC_INTEL_CSE_LITE_SKU
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# select SOC_INTEL_CSE_SEND_EOP_ASYNC
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select SOC_INTEL_COMMON_BLOCK_USB4
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select SOC_INTEL_COMMON_BLOCK_TCSS
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE
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select SOC_INTEL_CRASHLOG
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select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1
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config BOARD_GOOGLE_BASEBOARD_BROX
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def_bool n
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select BOARD_GOOGLE_BROX_COMMON
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_AUDIO_SOF
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select DRIVERS_GFX_GENERIC
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select HAVE_SLP_S0_GATE
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select MEMORY_SOLDERDOWN
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select SOC_INTEL_COMMON_BLOCK_IPU
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select SOC_INTEL_CRASHLOG
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select SOC_INTEL_RAPTORLAKE
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select SOC_INTEL_ALDERLAKE_PCH_P
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select DRIVERS_INTEL_ISH
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select SYSTEM_TYPE_LAPTOP
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select TPM_GOOGLE_TI50
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config BOARD_GOOGLE_BROX
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select BOARD_GOOGLE_BASEBOARD_BROX
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if BOARD_GOOGLE_BROX_COMMON
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config BASEBOARD_DIR
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string
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default "brox" if BOARD_GOOGLE_BASEBOARD_BROX
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config CHROMEOS
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select HAS_RECOVERY_MRC_CACHE
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config CHROMEOS_WIFI_SAR
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bool "Enable SAR options for ChromeOS build"
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depends on CHROMEOS
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select DSAR_ENABLE
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select GEO_SAR_ENABLE
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select SAR_ENABLE
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select USE_SAR
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config DEVICETREE
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default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x4 if BOARD_GOOGLE_BROX
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x50
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 66 # GPE0_DW2_02 (GPP_E2)
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAINBOARD_DIR
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default "google/brox"
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config MAINBOARD_FAMILY
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string
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default "Google_Brox" if BOARD_GOOGLE_BASEBOARD_BROX
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config MAINBOARD_PART_NUMBER
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default "Brox" if BOARD_GOOGLE_BROX
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config VARIANT_DIR
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default "brox" if BOARD_GOOGLE_BROX
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config VBOOT
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select VBOOT_EARLY_EC_SYNC
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select VBOOT_LID_SWITCH
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config DIMM_SPD_SIZE
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default 512
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config UART_FOR_CONSOLE
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int
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default 0
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config HAVE_WWAN_POWER_SEQUENCE
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def_bool n
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help
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Select this if the variant has a WWAN module and requires the poweroff sequence
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to be performed on shutdown. Must define WWAN_FCPO, WWAN_RST and WWAN_PERST GPIOs
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in variant.h, as well as T1_OFF_MS (time between PERST & RST) and T2_OFF_MS (time
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between RST and FCPO). WWAN_PERST and T1_OFF_MS are only necessary for PCIe WWAN
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(when HAVE_PCIE_WWAN is also selected).
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config HAVE_PCIE_WWAN
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def_bool n
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config USE_PM_ACPI_TIMER
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default y if BOARD_GOOGLE_PRIMUS4ES
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default n
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config MEMORY_SODIMM
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def_bool n
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select SPD_CACHE_ENABLE
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select SPD_CACHE_IN_FMAP
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config MEMORY_SOLDERDOWN
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def_bool n
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
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select HAVE_SPD_IN_CBFS
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config HAVE_SLP_S0_GATE
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def_bool n
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config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
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int
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default 33
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endif # BOARD_GOOGLE_BROX_COMMON
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