13a500a404
Change-Id: I2cce52561d30e30e1c81752cd2a455e7211006eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
61 lines
2.7 KiB
C
61 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdlib.h>
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#include <cpu/amd/lxdef.h>
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#include <cpu/x86/msr.h>
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#include <northbridge/amd/lx/northbridge.h>
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static const msrinit_t msr_table[] =
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{
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{CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB.
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* Rom Properties: Write Serialize, WriteProtect.
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* RomBase: 0xFFFC0
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* SysTop to RomBase Properties: Write Back.
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* SysTop: 0x000A0
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* System Memory Properties: (Write Back) */
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{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
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{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
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{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
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/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
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{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
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{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
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{MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
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{MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
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{MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
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{MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
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/* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.
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* It doesn't really matter in fact how much, however, because the only usage
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* of this extended memory will be to host the ramstage stage at RAMBASE,
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* currently 1Mb.
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* These registers will be set to their correct value by the Northbridge init code.
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*
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* WARNING: if ramstage could not be loaded, these registers are probably
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* incorrectly set here. You may comment the following two lines and set RAMBASE
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* to 0x4000 to revert to the previous behavior for LX-boards.
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*/
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{MSR_GLIU0_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
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{MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
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};
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void lx_msr_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(msr_table); i++)
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wrmsr(msr_table[i].index, msr_table[i].msr);
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}
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