13dee2a911
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default in coreboot and FSP. Even if FSP's default was 1, coreboot would reset it. This can lead to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "unaligned write" errors in Linux - ... At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms. To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable statically. There is no valid reason to disable it, which might break SATA, anyway. Currently, there are no reported issues on CML and CNL, so a change there could not be tested reliably. SKL/KBL was tested successfully without any noticable downsides. Thus, only SKL gets changed for now. Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
177 lines
6.0 KiB
Plaintext
177 lines
6.0 KiB
Plaintext
chip soc/intel/skylake
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# Enable Panel as eDP and configure power delays
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register "gpu_pp_up_delay_ms" = "210" # T3
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register "gpu_pp_down_delay_ms" = "500" # T10
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register "gpu_pp_cycle_delay_ms" = "5000" # T12
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register "gpu_pp_backlight_on_delay_ms" = "1" # T7
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register "gpu_pp_backlight_off_delay_ms" = "200" # T9
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "1"
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register "deep_s3_enable_dc" = "1"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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register "eist_enable" = "1"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_C"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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register "gen1_dec" = "0x000c0081"
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register "gen2_dec" = "0x000c0681"
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register "gen3_dec" = "0x000c1641"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Disable DPTF
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register "dptf_enable" = "0"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "1"
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register "SataSalpSupport" = "1"
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register "SataMode" = "0"
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# The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[0]" = "1"
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register "SataPortsDevSlp[1]" = "1"
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register "SataPortsDevSlp[2]" = "1"
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register "EnableAzalia" = "1"
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register "DspEnable" = "0"
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register "IoBufferOwnership" = "0"
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register "EnableTraceHub" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "0"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "0"
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register "PttSwitch" = "0"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "1"
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register "SaGv" = "SaGv_Enabled"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "3" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "0"
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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register "PmConfigPciClockRun" = "1"
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# Enable Root Ports 3, 4 and 9
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register "PcieRpEnable[2]" = "1" # Ethernet controller
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register "PcieRpClkReqSupport[2]" = "1"
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register "PcieRpClkReqNumber[2]" = "0"
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register "PcieRpClkSrcNumber[2]" = "0"
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register "PcieRpAdvancedErrorReporting[2]" = "1"
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register "PcieRpLtrEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1" # Wireless controller
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register "PcieRpClkReqSupport[3]" = "1"
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register "PcieRpClkReqNumber[3]" = "1"
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register "PcieRpClkSrcNumber[3]" = "1"
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register "PcieRpAdvancedErrorReporting[3]" = "1"
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register "PcieRpLtrEnable[3]" = "1"
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register "PcieRpEnable[8]" = "1" # NVMe controller
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register "PcieRpClkReqSupport[8]" = "1"
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register "PcieRpClkReqNumber[8]" = "4"
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register "PcieRpClkSrcNumber[8]" = "4"
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register "PcieRpAdvancedErrorReporting[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
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register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
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register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR
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register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
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register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT
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register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
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register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
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# PL1 override 25W
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register "tdp_pl1_override" = "25"
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# PL2 override 44W
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register "tdp_pl2_override" = "44"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 on end # PCI Express Port 3
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device pci 1c.3 on end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1f.0 on
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chip ec/51nb/npce985la0dx
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device pnp 0c09.0 on end
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device pnp 4e.5 on end
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device pnp 4e.6 on end
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device pnp 4e.11 on end
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end
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end # LPC Interface
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device pci 1f.1 off end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 off end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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