1410c2d219
In a mainboard's Config.lb file you can configure whether the primary and/or secondary IDE interfaces shall be enabled. Also, various fixups in the rest of the southbridge code, most notably the early SMBus code, plus some documentation improvements. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey_osgood@verizon.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOUTHBRIDGE_INTEL_I82371EB_H
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#define SOUTHBRIDGE_INTEL_I82371EB_H
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#ifndef __ROMCC__
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#include "chip.h"
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void i82371eb_enable(device_t dev);
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#endif
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#define PCICMD 0x04 /* PCI Command Register */
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#define XBCS 0x4e /* X-Bus Chip Select register */
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/* SMBus */
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#define SMBBA 0x90 /* SMBus Base Address */
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#define SMBHSTCFG 0xd2 /* SMBus Host Configuration */
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/* IDE */
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#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */
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#define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */
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/* Bit definitions */
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#define IOSE (1 << 0) /* I/O Space Enable */
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#define SMB_HST_EN (1 << 0) /* Host Interface Enable */
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#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */
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#endif /* SOUTHBRIDGE_INTEL_I82371EB_H */
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