14df2ef729
Refactor function mtk_spi_set_gpio_pinmux to reduce compiled code size. This change can save us about 552 bytes (before compression). Idea from Julius's comment in https://review.coreboot.org/c/coreboot/+/27498/4 BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I93bc88c535b6a2ff94e85f247cf2d51f60b9b29c Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <assert.h>
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#include <spi_flash.h>
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#include <soc/addressmap.h>
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#include <soc/flash_controller.h>
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#include <soc/gpio.h>
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#include <soc/spi.h>
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struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
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{
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.regs = (void *)SPI0_BASE,
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},
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{
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.regs = (void *)SPI1_BASE,
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},
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{
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.regs = (void *)SPI2_BASE,
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},
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{
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.regs = (void *)SPI3_BASE,
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},
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{
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.regs = (void *)SPI4_BASE,
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},
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{
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.regs = (void *)SPI5_BASE,
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}
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};
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struct pad_func {
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u8 pin_id;
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u8 func;
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};
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#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func}
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static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = {
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{
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PAD_FUNC(SPI_MI, SPI0_MI),
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PAD_FUNC(SPI_CSB, SPI0_CSB),
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PAD_FUNC(SPI_MO, SPI0_MO),
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PAD_FUNC(SPI_CLK, SPI0_CLK),
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},
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{
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PAD_FUNC(SPI1_MI, SPI1_A_MI),
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PAD_FUNC(SPI1_CSB, SPI1_A_CSB),
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PAD_FUNC(SPI1_MO, SPI1_A_MO),
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PAD_FUNC(SPI1_CLK, SPI1_A_CLK),
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},
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{
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PAD_FUNC(KPCOL1, SPI2_MI),
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PAD_FUNC(EINT0, SPI2_CSB),
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PAD_FUNC(EINT1, SPI2_MO),
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PAD_FUNC(EINT2, SPI2_CLK),
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},
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{
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PAD_FUNC(DPI_D8, SPI3_MI),
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PAD_FUNC(DPI_D9, SPI3_CSB),
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PAD_FUNC(DPI_D10, SPI3_MO),
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PAD_FUNC(DPI_D11, SPI3_CLK),
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},
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{
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PAD_FUNC(DPI_D4, SPI4_MI),
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PAD_FUNC(DPI_D5, SPI4_CSB),
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PAD_FUNC(DPI_D6, SPI4_MO),
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PAD_FUNC(DPI_D7, SPI4_CLK),
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},
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{
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PAD_FUNC(DPI_D0, SPI5_MI),
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PAD_FUNC(DPI_D1, SPI5_CSB),
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PAD_FUNC(DPI_D2, SPI5_MO),
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PAD_FUNC(DPI_D3, SPI5_CLK),
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}
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};
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static const struct pad_func bus1_pad1_funcs[4] = {
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PAD_FUNC(EINT7, SPI1_B_MI),
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PAD_FUNC(EINT8, SPI1_B_CSB),
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PAD_FUNC(EINT9, SPI1_B_MO),
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PAD_FUNC(EINT10, SPI1_B_CLK),
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};
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void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
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{
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assert(bus < SPI_BUS_NUMBER);
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const struct pad_func *ptr;
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if (pad_select == SPI_PAD0_MASK) {
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ptr = pad0_funcs[bus];
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} else {
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assert(bus == 1 && pad_select == SPI_PAD1_MASK);
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ptr = bus1_pad1_funcs;
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}
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for (int i = 0; i < 4; i++)
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gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
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}
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void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks)
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{
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write32(®s->spi_cfg0_reg,
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((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
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((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
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write32(®s->spi_cfg2_reg,
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((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
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((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
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clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK,
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((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
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}
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const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
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{
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.ctrlr = &spi_ctrlr,
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.bus_start = 0,
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.bus_end = SPI_BUS_NUMBER - 1,
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},
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};
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const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
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