1526b9f570
Change-Id: I2e1f04790b85e318bc1dc62e3590d9be2ee5ef52 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7378 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
84 lines
2.8 KiB
C
84 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SB700_H
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#define SB700_H
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#include <device/pci_ids.h>
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#include "chip.h"
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/* Power management index/data registers */
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#define BIOSRAM_INDEX 0xcd4
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#define BIOSRAM_DATA 0xcd5
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#define PM_INDEX 0xcd6
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#define PM_DATA 0xcd7
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#define PM2_INDEX 0xcd0
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#define PM2_DATA 0xcd1
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#define SB700_ACPI_IO_BASE 0x800
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#define ACPI_PM_EVT_BLK (SB700_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define ACPI_PM1_CNT_BLK (SB700_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x0E) /* 1 byte */
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#define ACPI_PM_TMR_BLK (SB700_ACPI_IO_BASE + 0x18) /* 4 bytes */
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#define ACPI_GPE0_BLK (SB700_ACPI_IO_BASE + 0x10) /* 8 bytes */
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#define ACPI_CPU_CONTROL (SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */
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extern void pm_iowrite(u8 reg, u8 value);
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extern u8 pm_ioread(u8 reg);
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extern void pm2_iowrite(u8 reg, u8 value);
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extern u8 pm2_ioread(u8 reg);
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extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
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#define REV_SB700_A11 0x11
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#define REV_SB700_A12 0x12
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#define REV_SB700_A14 0x14
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#define REV_SB700_A15 0x15
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/* This shouldn't be called before set_sb700_revision() is called.
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* Once set_sb700_revision() is called, we use get_sb700_revision(),
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* the simpler one, to get the sb700 revision ID.
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* The id is 0x39 if A11, 0x3A if A12, 0x3C if A14, 0x3D if A15.
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* The differentiate is 0x28, isn't it? */
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#define get_sb700_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28)
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void sb7xx_51xx_enable(device_t dev);
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#ifdef __PRE_RAM__
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void sb7xx_51xx_lpc_port80(void);
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void sb7xx_51xx_pci_port80(void);
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void sb7xx_51xx_lpc_init(void);
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void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);
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void sb7xx_51xx_disable_wideio(u8 wio_index);
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void sb7xx_51xx_early_setup(void);
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void sb7xx_51xx_before_pci_init(void);
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#else
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#include <device/pci.h>
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/* allow override in mainboard.c */
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void sb7xx_51xx_setup_sata_phys(struct device *dev);
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#endif
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int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
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int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
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u32 get_sbdn(u32 bus);
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void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn);
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#endif /* SB700_H */
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