15843bdad0
Add I2C chip initialization for the Galileo boards. TEST=Build and run on Galileo Gen2 Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14829 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
100 lines
3.7 KiB
C
100 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Jumper J2 determines the slave address of Cypress I/O GPIO expander */
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#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5
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static const struct reg_script gen1_gpio_init[] = {
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/* Initialize the legacy GPIO controller */
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x21),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x14),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
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/* Initialize the GPIO controller */
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REG_GPIO_WRITE(GPIO_INTEN, 0),
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REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
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REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
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REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 0x15),
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REG_GPIO_WRITE(GPIO_INTMASK, 0),
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REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
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REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
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REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
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REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
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/* Toggle the Cypress reset line */
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REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4),
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REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4),
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REG_SCRIPT_END
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};
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static const struct reg_script gen1_i2c_0x20_init[] = {
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/* Route I2C pins to Arduino header:
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* Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
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*
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* I2C_SDA -> ANALOG_A4
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* I2C_SCL -> ANALOG_A5
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*/
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 1),
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REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
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/* Set all GPIO expander pins connected to the Reset Button as inputs
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* Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
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* (GPORT5_BIT1) as inputs
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*/
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5),
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REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
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REG_SCRIPT_END
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};
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static const struct reg_script gen1_i2c_0x21_init[] = {
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/* Route I2C pins to Arduino header:
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* Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
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*
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* I2C_SDA -> ANALOG_A4
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* I2C_SCL -> ANALOG_A5
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*/
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 1),
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REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
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REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
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/* Set all GPIO expander pins connected to the Reset Button as inputs
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* Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
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* (GPORT5_BIT1) as inputs
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*/
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REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5),
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REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
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REG_SCRIPT_END
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};
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