1602dd5fdd
southbridge now: From: Morgan Tsai <my_tsai@sis.com> It supports SiS761GX / SiS966 chipset, only for AMD K8 platform so far. Due to integrated VGA sharing system memory, some code in southbridge folder have to init northbridge. Copyright (C) 2007 Morgan Tsai <my_tsai@sis.com> Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) Change Log: Newly support GIGABYTE GA-2761GXDK CPU type: AMD AM2 socket Northbridge: SiS 761GX Southbridge: SiS 966 SuperIO: ITE8716F Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
40 lines
1.3 KiB
C
40 lines
1.3 KiB
C
/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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* Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
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* Written by Morgan Tsai <my_tsai@sis.com> for SiS.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SIS966_CHIP_H
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#define SIS966_CHIP_H
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struct southbridge_sis_sis966_config
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{
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unsigned int ide0_enable : 1;
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unsigned int ide1_enable : 1;
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unsigned int sata0_enable : 1;
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unsigned int sata1_enable : 1;
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unsigned int mac_eeprom_smbus;
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unsigned int mac_eeprom_addr;
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};
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struct chip_operations;
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extern struct chip_operations southbridge_sis_sis966_ops;
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#endif /* SIS966_CHIP_H */
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