16246ea9ce
Since RTC is now a Kconfig ensure RTC is selected on the x86 chipsets which are in Chrome OS devices. This allows the eventlog to have proper timestamps instead of all zeros. BUG=chrome-os-partner:55993 Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16086 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
103 lines
2.7 KiB
Plaintext
103 lines
2.7 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOUTHBRIDGE_INTEL_BD82X6X
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bool
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config SOUTHBRIDGE_INTEL_C216
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bool
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if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
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config SOUTH_BRIDGE_OPTIONS # dummy
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select SOUTHBRIDGE_INTEL_COMMON
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select IOAPIC
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select HAVE_HARD_RESET
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select HAVE_USBDEBUG_OPTIONS
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select HAVE_SMI_HANDLER
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select USE_WATCHDOG_ON_BOOT
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select SPI_FLASH
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select COMMON_FADT
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select ACPI_SATA_GENERATOR
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select HAVE_INTEL_FIRMWARE
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select SOUTHBRIDGE_INTEL_COMMON_GPIO
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select RTC
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config EHCI_BAR
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hex
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default 0xfef00000
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config DRAM_RESET_GATE_GPIO
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int
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default 60
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/bd82x6x/bootblock.c"
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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help
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If you set this option to y, the serial IRQ machine will be
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operated in continuous mode.
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config HPET_MIN_TICKS
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hex
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default 0x80
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config HAVE_IFD_BIN
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def_bool y
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config BUILD_WITH_FAKE_IFD
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def_bool !HAVE_IFD_BIN
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endif
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if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK
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choice
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prompt "Flash ROM locking on S3 resume"
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default LOCK_SPI_ON_RESUME_NONE
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config LOCK_SPI_ON_RESUME_NONE
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bool "Don't lock ROM sections on S3 resume"
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config LOCK_SPI_ON_RESUME_RO
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bool "Lock all flash ROM sections on S3 resume"
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help
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If the flash ROM shall be protected against write accesses from the
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operating system (OS), the locking procedure has to be repeated after
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each resume from S3. Select this if you never want to update the flash
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ROM from within your OS. Notice: Even with this option, the write lock
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has still to be enabled on the normal boot path (e.g. by the payload).
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config LOCK_SPI_ON_RESUME_NO_ACCESS
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bool "Lock and disable reads all flash ROM sections on S3 resume"
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help
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If the flash ROM shall be protected against all accesses from the
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operating system (OS), the locking procedure has to be repeated after
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each resume from S3. Select this if you never want to update the flash
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ROM from within your OS. Notice: Even with this option, the lock
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has still to be enabled on the normal boot path (e.g. by the payload).
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endchoice
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endif
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