164dbd6a5c
Do this to wipe error message and hexdump of SPD from console log. Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11900 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
249 lines
6.2 KiB
Plaintext
249 lines
6.2 KiB
Plaintext
#
|
|
# This file is part of the coreboot project.
|
|
#
|
|
# This program is free software; you can redistribute it and/or modify
|
|
# it under the terms of the GNU General Public License as published by
|
|
# the Free Software Foundation; version 2 of the License.
|
|
#
|
|
# This program is distributed in the hope that it will be useful,
|
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
# GNU General Public License for more details.
|
|
#
|
|
# You should have received a copy of the GNU General Public License
|
|
# along with this program; if not, write to the Free Software
|
|
# Foundation, Inc.
|
|
|
|
# HYNIX-H5TQ2G83CFR
|
|
|
|
# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down
|
|
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
|
|
# bits[3:0]: 1 = 128 SPD Bytes Used
|
|
# bits[6:4]: 1 = 256 SPD Bytes Total
|
|
# bit7 : 0 = CRC covers bytes 0 ~ 125
|
|
11
|
|
|
|
# 1 SPD Revision -
|
|
# 0x10 = Revision 1.0
|
|
10
|
|
# 2 Key Byte / DRAM Device Type
|
|
# bits[7:0]: 0x0b = DDR3 SDRAM
|
|
0B
|
|
|
|
# 3 Key Byte / Module Type
|
|
# bits[3:0]: 3 = SO-DIMM
|
|
# bits[7:4]: reserved
|
|
03
|
|
|
|
# 4 SDRAM CHIP Density and Banks
|
|
# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
|
|
# bits[6:4]: 0 = 3 (8 banks)
|
|
# bit7 : reserved
|
|
03
|
|
|
|
# 5 SDRAM Addressing
|
|
# bits[2:0]: 1 = 10 Column Address Bits
|
|
# bits[5:3]: 3 = 15 Row Address Bits
|
|
# bits[7:6]: reserved
|
|
19
|
|
|
|
# 6 Module Nominal Voltage, VDD
|
|
# bit0 : 0 = 1.5 V operable
|
|
# bit1 : 0 = NOT 1.35 V operable
|
|
# bit2 : 0 = NOT 1.25 V operable
|
|
# bits[7:3]: reserved
|
|
00
|
|
|
|
# 7 Module Organization
|
|
# bits[2:0]: 1 = 8 bits
|
|
# bits[5:3]: 0 = 1 Rank
|
|
# bits[7:6]: reserved
|
|
01
|
|
|
|
# 8 Module Memory Bus Width
|
|
# bits[2:0]: 3 = Primary bus width is 64 bits
|
|
# bits[4:3]: 0 = 0 bits (no bus width extension)
|
|
# bits[7:5]: reserved
|
|
03
|
|
|
|
# 9 Fine Timebase (FTB) Dividend / Divisor
|
|
# bits[3:0]: 0x01 divisor
|
|
# bits[7:4]: 0x01 dividend
|
|
# 1 / 1 = 1.0 ps
|
|
11
|
|
|
|
# 10 Medium Timebase (MTB) Dividend
|
|
# 11 Medium Timebase (MTB) Divisor
|
|
# 1 / 8 = .125 ns
|
|
01 08
|
|
|
|
# 12 SDRAM Minimum Cycle Time (tCKmin)
|
|
# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
|
|
0C
|
|
|
|
# 13 Reserved
|
|
00
|
|
|
|
# 14 CAS Latencies Supported, Least Significant Byte
|
|
# 15 CAS Latencies Supported, Most Significant Byte
|
|
# Cas Latencies of 11 - 5 are supported
|
|
7E 00
|
|
|
|
# 16 Minimum CAS Latency Time (tAAmin)
|
|
# 0x6C = 13.5ns - DDR3-1333
|
|
6C
|
|
|
|
# 17 Minimum Write Recovery Time (tWRmin)
|
|
# 0x78 = tWR of 15ns - All DDR3 speed grades
|
|
78
|
|
|
|
# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
|
|
# 0x6E = 13.5ns - DDR3-1333
|
|
6C
|
|
|
|
# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
|
|
# 0x30 = 6ns
|
|
30
|
|
|
|
# 20 Minimum Row Precharge Delay Time (tRPmin)
|
|
# 0x6C = 13.5ns - DDR3-1333
|
|
6C
|
|
|
|
# 21 Upper Nibbles for tRAS and tRC
|
|
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
|
|
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
|
|
11
|
|
|
|
# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
|
|
# 0x120 = 36ns - DDR3-1333 (see byte 21)
|
|
20
|
|
|
|
# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
|
|
# 0x28C = 49.5ns - DDR3-1333
|
|
8C
|
|
|
|
# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
|
|
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
|
|
# 0x500 = 160ns - for 2 Gigabit chips
|
|
00 05
|
|
|
|
# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
|
|
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
|
|
3C
|
|
|
|
# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
|
|
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
|
|
3C
|
|
|
|
# 28 Upper Nibble for tFAWmin
|
|
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
|
|
# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
|
|
00 F0
|
|
|
|
# 30 SDRAM Optional Feature
|
|
# bit0 : 1= RZQ/6 supported
|
|
# bit1 : 1 = RZQ/7 supported
|
|
# bits[6:2]: reserved
|
|
# bit7 : 1 = DLL Off mode supported
|
|
83
|
|
|
|
# 31 SDRAM Thermal and Refresh Options
|
|
# bit0 : 1 = Temp up to 95c supported
|
|
# bit1 : 0 = 85-95c uses 2x refresh rate
|
|
# bit2 : 1 = Auto Self Refresh supported
|
|
# bit3 : 0 = no on die thermal sensor
|
|
# bits[6:4]: reserved
|
|
# bit7 : 0 = partial self refresh supported
|
|
05
|
|
|
|
# 32 Module Thermal Sensor
|
|
# 0 = Thermal sensor not incorporated onto this assembly
|
|
00
|
|
|
|
# 33 SDRAM Device Type
|
|
# bits[1:0]: 2 = Signal Loading
|
|
# bits[3:2]: reserved
|
|
# bits[6:4]: 4 = Die count
|
|
# bit7 : 0 = Standard Monolithic DRAM Device
|
|
42
|
|
|
|
# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
|
|
# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
|
|
# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
|
|
# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
|
|
# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
|
|
00 00 00 00 00
|
|
|
|
# 39 (reserved)
|
|
00
|
|
|
|
# 40 - 47 (reserved)
|
|
00 00 00 00 00 00 00 00
|
|
|
|
# 48 - 55 (reserved)
|
|
00 00 00 00 00 00 00 00
|
|
|
|
# 56 - 59 (reserved)
|
|
00 00 00 00
|
|
|
|
# 60 Raw Card Extension, Module Nominal Height
|
|
# bits[4:0]: 0 = <= 15mm tall
|
|
# bits[7:5]: 0 = raw card revision 0-3
|
|
00
|
|
|
|
# 61 Module Maximum Thickness
|
|
# bits[3:0]: 0 = thickness front <= 1mm
|
|
# bits[7:4]: 0 = thinkness back <= 1mm
|
|
00
|
|
|
|
# 62 Reference Raw Card Used
|
|
# bits[4:0]: 0 = Reference Raw card A used
|
|
# bits[6:5]: 0 = revision 0
|
|
# bit7 : 0 = Reference raw cards A through AL
|
|
00
|
|
|
|
# 63 Address Mapping from Edge Connector to DRAM
|
|
# bit0 : 0 = standard mapping (not mirrored)
|
|
# bits[7:1]: reserved
|
|
00
|
|
|
|
# 64 - 71 (reserved)
|
|
00 00 00 00 00 00 00 00
|
|
|
|
# 72 - 79 (reserved)
|
|
00 00 00 00 00 00 00 00
|
|
|
|
# 80 - 87 (reserved)
|
|
00 00 00 00 00 00 00 00
|
|
|
|
# 88 - 95 (reserved)
|
|
00 00 00 00 00 00 00 00
|
|
|
|
# 96 - 103 (reserved)
|
|
00 00 00 00 00 00 00 00
|
|
|
|
# 104 - 111 (reserved)
|
|
00 00 00 00 00 00 00 00
|
|
|
|
# 112 - 116 (reserved)
|
|
00 00 00 00 00
|
|
|
|
# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
|
|
# 0x0001 = AMD
|
|
00 01
|
|
|
|
# 119 Module ID: Module Manufacturing Location - oem specified
|
|
00
|
|
|
|
# 120 Module ID: Module Manufacture Year in BCD
|
|
# 0x13 = 2013
|
|
# 121 Module ID: Module Manufacture week
|
|
# 0x12 = 12th week
|
|
13 12
|
|
|
|
# 122 - 125: Module Serial Number
|
|
00 00 00 00
|
|
|
|
# 126 - 127: Cyclical Redundancy Code
|
|
c4 1b
|