166932c5c0
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Bilby, Birman, Chausie and Majolica. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/amd_pci_util.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <soc/acpi.h>
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#include <string.h>
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#include <types.h>
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#include "gpio.h"
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/*
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*/
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static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
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static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
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/*
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* This controls the device -> IRQ routing.
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*
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* Hardcoded IRQs:
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* 0: timer < soc/amd/common/acpi/lpc.asl
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* 1: i8042 - Keyboard
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* 2: cascade
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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*/
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static const struct fch_irq_routing fch_irq_map[] = {
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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{ PIRQ_D, 12, PIRQ_NC },
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{ PIRQ_E, 14, PIRQ_NC },
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{ PIRQ_F, 15, PIRQ_NC },
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{ PIRQ_G, 12, PIRQ_NC },
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{ PIRQ_H, 14, PIRQ_NC },
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{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
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{ PIRQ_SD, PIRQ_NC, PIRQ_NC },
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{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
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{ PIRQ_EMMC, PIRQ_NC, PIRQ_NC },
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{ PIRQ_GPIO, 11, 11 },
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{ PIRQ_I2C0, 10, 10 },
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{ PIRQ_I2C1, 7, 7 },
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{ PIRQ_I2C2, 6, 6 },
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{ PIRQ_I2C3, 5, 5 },
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{ PIRQ_UART0, 4, 4 },
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{ PIRQ_UART1, 3, 3 },
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/* The MISC registers are not interrupt numbers */
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{ PIRQ_MISC, 0xfa, 0x00 },
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{ PIRQ_MISC0, 0x91, 0x00 },
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{ PIRQ_HPET_L, 0x00, 0x00 },
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{ PIRQ_HPET_H, 0x00, 0x00 },
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};
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static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
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{
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*length = ARRAY_SIZE(fch_irq_map);
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return fch_irq_map;
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}
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static void init_tables(void)
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{
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const struct fch_irq_routing *mb_irq_map;
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size_t mb_fch_irq_mapping_table_size;
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size_t i;
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mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
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memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
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memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
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for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
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if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
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printk(BIOS_WARNING,
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"Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
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mb_irq_map[i].intr_index, i);
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continue;
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}
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fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
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fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
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}
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}
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static void pirq_setup(void)
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{
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intr_data_ptr = fch_apic_routing;
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picr_data_ptr = fch_pic_routing;
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}
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static void mainboard_init(void *chip_info)
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{
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mainboard_program_gpios();
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}
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static void mainboard_enable(struct device *dev)
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{
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init_tables();
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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