16c851fa9a
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1d42341e9cf5e35142f9cc8e97a03e442655bc13 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <device/mmio.h>
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#include <bootblock_common.h>
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#include <delay.h>
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#include <soc/grf.h>
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#include <gpio.h>
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#include <soc/clock.h>
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#include <soc/i2c.h>
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#include <soc/pwm.h>
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#include <soc/spi.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "board.h"
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#include "pwm_regulator.h"
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void bootblock_mainboard_early_init(void)
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{
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/* Configure all programmable IO voltage domains (3D/4A and 2A/2B) early
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so that we know we can use our GPIOs reliably in following code. */
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write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1 | 1 << 0));
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/* On Scarlet-based boards, the 4C/4D domain is 1.8V (on others 3.0V) */
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if (CONFIG(GRU_BASEBOARD_SCARLET))
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write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 3));
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/* Reconfigure GPIO1 from dynamic voltage selection through GPIO0_B1 to
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hardcoded 1.8V, and change that pin to a normal GPIO. The TRM says
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this is already the power-on reset, but we all know that TRMs lie. */
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write32(&rk3399_pmugrf->soc_con0, RK_SETBITS(1 << 9 | 1 << 8));
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write32(&rk3399_pmugrf->gpio0b_iomux, RK_CLRBITS(3 << 2));
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/* Enable rails powering GPIO blocks, among other things. */
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gpio_output(GPIO_P30V_EN, 1);
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if (!CONFIG(GRU_BASEBOARD_SCARLET))
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gpio_output(GPIO_P15V_EN, 1); /* Scarlet: EC-controlled */
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if (CONFIG(CONSOLE_SERIAL)) {
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_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
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"CONSOLE_SERIAL_UART should be UART2");
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/* iomux: select gpio4c[4:3] as uart2 dbg port */
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write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
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/* grf soc_con7[11:10] use for uart2 select */
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write32(&rk3399_grf->soc_con7, UART2C_SEL);
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}
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}
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static void configure_spi_flash(void)
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{
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gpio_input(GPIO(1, A, 7)); /* SPI1_MISO remove pull-up */
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gpio_input(GPIO(1, B, 0)); /* SPI1_MOSI remove pull-up */
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gpio_input(GPIO(1, B, 1)); /* SPI1_CLK remove pull-up */
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gpio_input(GPIO(1, B, 2)); /* SPI1_CS remove pull-up */
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rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33*MHz);
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rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5);
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write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
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write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
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}
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static void configure_ec(void)
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{
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gpio_input(GPIO(2, C, 4)); /* SPI5_MISO remove pull-up */
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gpio_input(GPIO(2, C, 5)); /* SPI5_MOSI remove pull-up */
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gpio_input(GPIO(2, C, 6)); /* SPI5_CLK remove pull-up */
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gpio_input_pullup(GPIO(2, C, 7)); /* SPI5_CS confirm pull-up */
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750);
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write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);
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}
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static void configure_tpm(void)
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{
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if (CONFIG(GRU_HAS_TPM2)) {
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rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
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if (CONFIG(GRU_BASEBOARD_SCARLET)) {
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gpio_input(GPIO(2, B, 1)); /* SPI2_MISO no-pull */
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gpio_input(GPIO(2, B, 2)); /* SPI2_MOSI no-pull */
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gpio_input(GPIO(2, B, 3)); /* SPI2_CLK no-pull */
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gpio_input_pullup(GPIO(2, B, 4)); /* SPI2_CS */
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write32(&rk3399_grf->iomux_spi2, IOMUX_SPI2);
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} else {
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gpio_input(GPIO(3, A, 4)); /* SPI0_MISO no-pull */
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gpio_input(GPIO(3, A, 5)); /* SPI0_MOSI no-pull */
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gpio_input(GPIO(3, A, 6)); /* SPI0_CLK no-pull */
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gpio_input_pullup(GPIO(3, A, 7)); /* SPI0_CS */
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write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
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}
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gpio_input_irq(GPIO_TPM_IRQ, IRQ_TYPE_EDGE_RISING, GPIO_PULLUP);
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} else {
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gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull-up */
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gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull-up */
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i2c_init(0, 400*KHz);
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write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
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write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
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}
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}
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static void speed_up_boot_cpu(void)
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{
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pwm_regulator_configure(PWM_REGULATOR_LIT, 1150);
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udelay(200);
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rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE);
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}
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void bootblock_mainboard_init(void)
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{
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speed_up_boot_cpu();
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if (rkclk_was_watchdog_reset())
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reboot_from_watchdog();
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configure_spi_flash();
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configure_ec();
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configure_tpm();
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setup_chromeos_gpios();
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}
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