16e32ed2f3
This adds a directory with files copied over from Jerry, in addition to build system related changes (configs/* and Kconfig stuff) necessary to emerge-veyron_brain coreboot. The next patch will account for differences between Jerry and Brain. BUG=none BRANCH=none TEST=emerge-veyron_brain coreboot works Change-Id: Ib0da9caf80f46991b96bcb5756f807237f0902e1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9509d6277dae25a78062c1301054a39f704b33fe Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I972f2623d9b0a43e3ea5312b3c4cd34ab44edc36 Original-Reviewed-on: https://chromium-review.googlesource.com/236989 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9637 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
42 lines
1.2 KiB
Makefile
42 lines
1.2 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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bootblock-y += bootblock.c
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bootblock-y += boardid.c
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bootblock-y += chromeos.c
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bootblock-y += reset.c
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verstage-y += boardid.c
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verstage-y += chromeos.c
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verstage-y += reset.c
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romstage-y += boardid.c
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romstage-y += romstage.c
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romstage-y += sdram_configs.c
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romstage-y += reset.c
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ramstage-y += boardid.c
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ramstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += reset.c
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bootblock-y += memlayout.ld
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verstage-y += memlayout.ld
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romstage-y += memlayout.ld
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ramstage-y += memlayout.ld
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