182dbdeac4
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <amdblocks/acpimmio.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "hudson.h"
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#include "imc.h"
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#include "smbus.h"
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#include "smi.h"
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#define PM_REG_USB_ENABLE 0xef
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enum usb_enable {
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USB_EN_DEVFN_12_0 = (1 << 0),
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USB_EN_DEVFN_12_2 = (1 << 1),
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USB_EN_DEVFN_13_0 = (1 << 2),
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USB_EN_DEVFN_13_2 = (1 << 3),
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USB_EN_DEVFN_16_0 = (1 << 4),
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USB_EN_DEVFN_16_2 = (1 << 5),
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};
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static void hudson_disable_usb(u8 disable)
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{
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u8 reg8;
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/* Bit 7 handles routing, 6 is reserved. we don't mess with those */
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disable &= 0x3f;
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reg8 = pm_read8(PM_REG_USB_ENABLE);
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reg8 &= ~disable;
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pm_write8(PM_REG_USB_ENABLE, reg8);
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}
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void hudson_enable(struct device *dev)
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{
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printk(BIOS_DEBUG, "hudson_enable()\n");
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(0x14, 5):
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if (dev->enabled == 0) {
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u32 usb_device_id = pci_read_config16(dev, PCI_DEVICE_ID);
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u8 reg8;
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if (usb_device_id == PCI_DEVICE_ID_AMD_SB900_USB_20_5) {
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/* turn off and remove device 0:14.5 from PCI space */
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reg8 = pm_read8(0xef);
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reg8 &= ~(1 << 6);
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pm_write8(0xef, reg8);
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}
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}
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break;
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case PCI_DEVFN(0x14, 7):
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if (dev->enabled == 0) {
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u32 sd_device_id = pci_read_config16(dev, PCI_DEVICE_ID);
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/* turn off the SDHC controller in the PM reg */
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u8 reg8;
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if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) {
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reg8 = pm_read8(0xe7);
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reg8 &= ~(1 << 0);
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pm_write8(0xe7, reg8);
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}
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else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) {
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reg8 = pm_read8(0xe8);
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reg8 &= ~(1 << 0);
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pm_write8(0xe8, reg8);
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}
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/* remove device 0:14.7 from PCI space */
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reg8 = pm_read8(0xd3);
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reg8 &= ~(1 << 6);
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pm_write8(0xd3, reg8);
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}
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break;
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/* Make sure to disable other functions if function 0 is disabled */
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case PCI_DEVFN(0x12, 0):
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if (dev->enabled == 0)
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hudson_disable_usb(USB_EN_DEVFN_12_0);
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/* fall through */
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case PCI_DEVFN(0x12, 2):
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if (dev->enabled == 0)
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hudson_disable_usb(USB_EN_DEVFN_12_2);
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break;
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case PCI_DEVFN(0x13, 0):
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if (dev->enabled == 0)
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hudson_disable_usb(USB_EN_DEVFN_13_0);
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/* fall through */
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case PCI_DEVFN(0x13, 2):
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if (dev->enabled == 0)
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hudson_disable_usb(USB_EN_DEVFN_13_2);
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break;
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case PCI_DEVFN(0x16, 0):
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if (dev->enabled == 0)
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hudson_disable_usb(USB_EN_DEVFN_16_0);
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/* fall through */
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case PCI_DEVFN(0x16, 2):
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if (dev->enabled == 0)
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hudson_disable_usb(USB_EN_DEVFN_16_2);
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break;
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default:
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break;
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}
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}
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static void hudson_init_acpi_ports(void)
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{
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/* We use some of these ports in SMM regardless of whether or not
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* ACPI tables are generated. Enable these ports indiscriminately.
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*/
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pm_write16(0x60, ACPI_PM_EVT_BLK);
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pm_write16(0x62, ACPI_PM1_CNT_BLK);
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pm_write16(0x64, ACPI_PM_TMR_BLK);
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pm_write16(0x68, ACPI_GPE0_BLK);
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/* CpuControl is in \_PR.CP00, 6 bytes */
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pm_write16(0x66, ACPI_CPU_CONTROL);
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if (CONFIG(HAVE_SMI_HANDLER)) {
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pm_write16(0x6a, ACPI_SMI_CTL_PORT);
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hudson_enable_acpi_cmd_smi();
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} else {
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pm_write16(0x6a, 0);
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}
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/* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
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* at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
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*/
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pm_write8(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2);
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}
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static void hudson_init(void *chip_info)
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{
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hudson_init_acpi_ports();
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}
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static void hudson_final(void *chip_info)
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{
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/* AMD AGESA does not enable thermal zone, so we enable it here. */
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if (CONFIG(HUDSON_IMC_FWM) &&
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!CONFIG(ACPI_ENABLE_THERMAL_ZONE))
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enable_imc_thermal_zone();
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}
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struct chip_operations southbridge_amd_agesa_hudson_ops = {
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CHIP_NAME("ATI HUDSON")
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.enable_dev = hudson_enable,
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.init = hudson_init,
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.final = hudson_final
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};
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