182dbdeac4
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "hudson.h"
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <bootstate.h>
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/*
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* Update the PCI devices with a valid IRQ number
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* that is set in the mainboard PCI_IRQ structures.
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*/
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static void set_pci_irqs(void *unused)
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{
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/* Write PCI_INTR regs 0xC00/0xC01 */
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write_pci_int_table();
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/* Write IRQs for all devicetree enabled devices */
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write_pci_cfg_irqs();
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}
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/*
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* Hook this function into the PCI state machine
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* on entry into BS_DEV_ENABLE.
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*/
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
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static struct pci_operations lops_pci = {
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.set_subsystem = 0,
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};
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static struct device_operations pci_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = DEVICE_NOOP,
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.scan_bus = pci_scan_bridge,
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.reset_bus = pci_bus_reset,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver pci_driver __pci_driver = {
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.ops = &pci_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_SB900_PCI,
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};
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