182dbdeac4
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
151 lines
3.2 KiB
C
151 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/smbus.h>
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#include <cpu/x86/lapic.h>
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#include <arch/ioapic.h>
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#include "hudson.h"
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#include "smbus.c"
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#define NMI_OFF 0
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define BIT0 (1 << 0)
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#define BIT1 (1 << 1)
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#define BIT2 (1 << 2)
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#define BIT3 (1 << 3)
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#define BIT4 (1 << 4)
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#define BIT5 (1 << 5)
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#define BIT6 (1 << 6)
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#define BIT7 (1 << 7)
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#define BIT8 (1 << 8)
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#define BIT9 (1 << 9)
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#define BIT10 (1 << 10)
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#define BIT11 (1 << 11)
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#define BIT12 (1 << 12)
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#define BIT13 (1 << 13)
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#define BIT14 (1 << 14)
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#define BIT15 (1 << 15)
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#define BIT16 (1 << 16)
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#define BIT17 (1 << 17)
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#define BIT18 (1 << 18)
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#define BIT19 (1 << 19)
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#define BIT20 (1 << 20)
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#define BIT21 (1 << 21)
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#define BIT22 (1 << 22)
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#define BIT23 (1 << 23)
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#define BIT24 (1 << 24)
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#define BIT25 (1 << 25)
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#define BIT26 (1 << 26)
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#define BIT27 (1 << 27)
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#define BIT28 (1 << 28)
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#define BIT29 (1 << 29)
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#define BIT30 (1 << 30)
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#define BIT31 (1 << 31)
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/*
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* HUDSON enables all USB controllers by default in SMBUS Control.
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* HUDSON enables SATA by default in SMBUS Control.
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*/
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static void sm_init(struct device *dev)
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{
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setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
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}
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static int lsmbus_recv_byte(struct device *dev)
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{
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u32 device;
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struct resource *res;
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struct bus *pbus;
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device = dev->path.i2c.device;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x90);
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return do_smbus_recv_byte(res->base, device);
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}
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static int lsmbus_send_byte(struct device *dev, u8 val)
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{
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u32 device;
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struct resource *res;
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struct bus *pbus;
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device = dev->path.i2c.device;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x90);
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return do_smbus_send_byte(res->base, device, val);
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}
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static int lsmbus_read_byte(struct device *dev, u8 address)
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{
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u32 device;
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struct resource *res;
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struct bus *pbus;
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device = dev->path.i2c.device;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x90);
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return do_smbus_read_byte(res->base, device, address);
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}
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static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
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{
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u32 device;
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struct resource *res;
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struct bus *pbus;
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device = dev->path.i2c.device;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x90);
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return do_smbus_write_byte(res->base, device, address, val);
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}
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static struct smbus_bus_operations lops_smbus_bus = {
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.recv_byte = lsmbus_recv_byte,
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.send_byte = lsmbus_send_byte,
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.read_byte = lsmbus_read_byte,
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.write_byte = lsmbus_write_byte,
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};
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static void hudson_sm_read_resources(struct device *dev)
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{
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}
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static void hudson_sm_set_resources(struct device *dev)
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{
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations smbus_ops = {
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.read_resources = hudson_sm_read_resources,
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.set_resources = hudson_sm_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sm_init,
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.scan_bus = scan_smbus,
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.ops_pci = &lops_pci,
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.ops_smbus_bus = &lops_smbus_bus,
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};
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static const struct pci_driver smbus_driver __pci_driver = {
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.ops = &smbus_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_SB900_SM,
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};
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