182dbdeac4
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
180 lines
6.0 KiB
C
180 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#ifndef HUDSON_H
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#define HUDSON_H
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#include <types.h>
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#include <device/device.h>
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/* Offsets from ACPI_MMIO_BASE
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* This is defined by AGESA, but we don't include AGESA headers to avoid
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* polluting the namespace.
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*/
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#define PM_MMIO_BASE 0xfed80300
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/* Power management index/data registers */
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#define BIOSRAM_INDEX 0xcd4
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#define BIOSRAM_DATA 0xcd5
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#define PM_INDEX 0xcd6
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#define PM_DATA 0xcd7
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#define PM2_INDEX 0xcd0
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#define PM2_DATA 0xcd1
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#define PM_ACPI_MMIO_EN 0x24
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#define PM_SERIRQ_CONF 0x54
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#define PM_EVT_BLK 0x60
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#define PM1_CNT_BLK 0x62
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#define PM_TMR_BLK 0x64
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#define PM_CPU_CTRL 0x66
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#define PM_GPE0_BLK 0x68
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#define PM_ACPI_SMI_CMD 0x6A
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#define PM_ACPI_CONF 0x74
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#define PM_PMIO_DEBUG 0xD2
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#define PM_MANUAL_RESET 0xD3
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#define PM_HUD_SD_FLASH_CTRL 0xE7
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#define PM_YANG_SD_FLASH_CTRL 0xE8
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#define PM_PCIB_CFG 0xEA
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#define HUDSON_ACPI_IO_BASE CONFIG_HUDSON_ACPI_IO_BASE
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#define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
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#define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */
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#define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
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#define ACPI_SMI_CTL_PORT 0xb2
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#define ACPI_SMI_CMD_CST_CONTROL 0xde
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#define ACPI_SMI_CMD_PST_CONTROL 0xad
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#define ACPI_SMI_CMD_DISABLE 0xbe
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#define ACPI_SMI_CMD_ENABLE 0xef
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#define ACPI_SMI_CMD_S4_REQ 0xc0
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#define REV_HUDSON_A11 0x11
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#define REV_HUDSON_A12 0x12
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#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
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#define ROUTE_TPM_2_SPI BIT(3)
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#define SPI_ROM_ENABLE 0x02
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#define SPI_BASE_ADDRESS 0xFEC10000
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#define LPC_IO_PORT_DECODE_ENABLE 0x44
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#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)
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#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1)
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#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2)
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#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3)
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#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4)
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#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5)
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#define DECODE_ENABLE_SERIAL_PORT0 BIT(6)
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#define DECODE_ENABLE_SERIAL_PORT1 BIT(7)
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#define DECODE_ENABLE_SERIAL_PORT2 BIT(8)
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#define DECODE_ENABLE_SERIAL_PORT3 BIT(9)
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#define DECODE_ENABLE_SERIAL_PORT4 BIT(10)
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#define DECODE_ENABLE_SERIAL_PORT5 BIT(11)
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#define DECODE_ENABLE_SERIAL_PORT6 BIT(12)
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#define DECODE_ENABLE_SERIAL_PORT7 BIT(13)
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#define DECODE_ENABLE_AUDIO_PORT0 BIT(14)
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#define DECODE_ENABLE_AUDIO_PORT1 BIT(15)
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#define DECODE_ENABLE_AUDIO_PORT2 BIT(16)
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#define DECODE_ENABLE_AUDIO_PORT3 BIT(17)
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#define DECODE_ENABLE_MIDI_PORT0 BIT(18)
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#define DECODE_ENABLE_MIDI_PORT1 BIT(19)
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#define DECODE_ENABLE_MIDI_PORT2 BIT(20)
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#define DECODE_ENABLE_MIDI_PORT3 BIT(21)
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#define DECODE_ENABLE_MSS_PORT0 BIT(22)
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#define DECODE_ENABLE_MSS_PORT1 BIT(23)
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#define DECODE_ENABLE_MSS_PORT2 BIT(24)
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#define DECODE_ENABLE_MSS_PORT3 BIT(25)
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#define DECODE_ENABLE_FDC_PORT0 BIT(26)
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#define DECODE_ENABLE_FDC_PORT1 BIT(27)
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#define DECODE_ENABLE_GAME_PORT BIT(28)
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#define DECODE_ENABLE_KBC_PORT BIT(29)
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#define DECODE_ENABLE_ACPIUC_PORT BIT(30)
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#define DECODE_ENABLE_ADLIB_PORT BIT(31)
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#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48
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#define LPC_WIDEIO2_ENABLE BIT(25)
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#define LPC_WIDEIO1_ENABLE BIT(24)
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#define LPC_WIDEIO0_ENABLE BIT(2)
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#define LPC_WIDEIO_GENERIC_PORT 0x64
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#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74
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#define LPC_ALT_WIDEIO2_ENABLE BIT(3)
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#define LPC_ALT_WIDEIO1_ENABLE BIT(2)
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#define LPC_ALT_WIDEIO0_ENABLE BIT(0)
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#define LPC_TRUSTED_PLATFORM_MODULE 0x7c
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#define TPM_12_EN BIT(0)
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#define TPM_LEGACY_EN BIT(2)
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#define LPC_WIDEIO2_GENERIC_PORT 0x90
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#define SPI_CNTRL0 0x00
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#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
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/* Nominal is 16.7MHz on older devices, 33MHz on newer */
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#define SPI_READ_MODE_NOM 0x00000000
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#define SPI_READ_MODE_DUAL112 ( BIT(29) )
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#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18))
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#define SPI_READ_MODE_DUAL122 (BIT(30) )
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#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))
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#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )
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/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */
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#define SPI_READ_MODE_FAST_HUDSON1 ( BIT(18))
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#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))
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#define SPI_ARB_ENABLE BIT(19)
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#define SPI_CNTRL1 0x0c
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/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */
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#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
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#define SPI_NORM_SPEED_SH 12
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#define SPI_FAST_SPEED_SH 8
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#define SPI100_ENABLE 0x20
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#define SPI_USE_SPI100 BIT(0)
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#define SPI100_SPEED_CONFIG 0x22
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#define SPI_SPEED_66M (0x0)
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#define SPI_SPEED_33M ( BIT(0))
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#define SPI_SPEED_22M ( BIT(1) )
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#define SPI_SPEED_16M ( BIT(1) | BIT(0))
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#define SPI_SPEED_100M (BIT(2) )
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#define SPI_SPEED_800K (BIT(2) | BIT(0))
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#define SPI_NORM_SPEED_NEW_SH 12
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#define SPI_FAST_SPEED_NEW_SH 8
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#define SPI_ALT_SPEED_NEW_SH 4
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#define SPI_TPM_SPEED_NEW_SH 0
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#define SPI100_HOST_PREF_CONFIG 0x2c
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#define SPI_RD4DW_EN_HOST BIT(15)
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static inline int hudson_sata_enable(void)
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{
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/* True if IDE or AHCI. */
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return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2);
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}
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static inline int hudson_ide_enable(void)
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{
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/* True if IDE or LEGACY IDE. */
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return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
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}
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void hudson_lpc_port80(void);
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void hudson_lpc_decode(void);
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void hudson_pci_port80(void);
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void hudson_clk_output_48Mhz(void);
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void hudson_read_mode(u32 mode);
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void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
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void hudson_disable_4dw_burst(void);
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void hudson_set_readspeed(u16 norm, u16 fast);
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void lpc_wideio_512_window(uint16_t base);
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void lpc_wideio_16_window(uint16_t base);
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void hudson_tpm_decode_spi(void);
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void configure_hudson_uart(void);
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void hudson_enable(struct device *dev);
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void s3_resume_init_data(void *FchParams);
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#endif /* HUDSON_H */
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