199b10fc21
Only 16 MByte of the SPI flash can be mapped right below the 4 GB boundary. In case of a larger SPI flash size, still only the 16 MByte region starting at 0xff000000 can be configured as WRPROT and be reserved for the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting at address 0xfe000000 contain for example the LAPIC MMIO region, the ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't be configured as WRPROT. Reserving this region for the MMIO mapped SPI flash would also result in an overlap with the MMIO resources mentioned above. In the case of a smaller SPI flash, reserving the full 16 MByte flash MMIO region makes sure that the resource allocator won't try to put anything else in the lower parts of the 16 MByte SPI mapping region. To avoid the issues described above, always reserve/cache the maximum amount of 16 MBytes of flash that can be mapped below 4 GB. TEST=On boards with 16 MByte SPI flash chips, the resulting image of a timeless build doesn't change with this patch. Verified this on Chausie (Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena (Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the resulting image of a timeless build is different, but neither the coreboot console output nor the Linux dmesg output shows any errors that might be related to this change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <smp/node.h>
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#include <bootblock_common.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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#include <amdblocks/amd_pci_mmconf.h>
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#include <amdblocks/biosram.h>
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#include <amdblocks/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/southbridge.h>
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#include <timestamp.h>
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#include <halt.h>
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#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000
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#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB"
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#endif
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#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000
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#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB"
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#endif
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/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */
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static void amd_initmmio(void)
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{
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msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
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int mtrr;
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/*
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* todo: AGESA currently writes variable MTRRs. Once that is
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* corrected, un-hardcode this MTRR.
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*
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* Be careful not to use get_free_var_mtrr/set_var_mtrr pairs
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* where all cores execute the path. Both cores within a compute
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* unit share MTRRs. Programming core0 has the appearance of
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* modifying core1 too. Using the pair again will create
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* duplicate copies.
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*/
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH;
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set_var_mtrr(mtrr, FLASH_BELOW_4GB_MAPPING_REGION_BASE,
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FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP;
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set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE,
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CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK);
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM;
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set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE,
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CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE);
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}
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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enable_pci_mmconf();
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amd_initmmio();
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/*
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* Call lib/bootblock.c main with BSP, shortcut for APs
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*/
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if (!boot_cpu()) {
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void (*ap_romstage_entry)(void) =
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(void (*)(void))get_ap_entry_ptr();
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ap_romstage_entry(); /* execution does not return */
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halt();
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}
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/* TSC cannot be relied upon. Override the TSC value passed in. */
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bootblock_main_with_basetime(timestamp_get());
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}
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void bootblock_soc_early_init(void)
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{
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bootblock_fch_early_init();
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post_code(0x90);
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}
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void bootblock_soc_init(void)
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{
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if (CONFIG(AMD_SOC_CONSOLE_UART))
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assert(CONFIG_UART_FOR_CONSOLE >= 0
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&& CONFIG_UART_FOR_CONSOLE <= 1);
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u32 val = cpuid_eax(1);
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printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
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bootblock_fch_init();
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}
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