199b75f58a
The RISC-V Privileged Architecture specification defines the Machine Time Registers (mtime and mtimecmp) in section 3.1.15. Makes it possible to use the generic udelay. The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc, sifive and ucb soc. Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27434 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
29 lines
443 B
Plaintext
29 lines
443 B
Plaintext
config SOC_UCB_RISCV
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select ARCH_RISCV
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select ARCH_BOOTBLOCK_RISCV
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select ARCH_VERSTAGE_RISCV
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select ARCH_ROMSTAGE_RISCV
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select ARCH_RAMSTAGE_RISCV
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select BOOTBLOCK_CONSOLE
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select GENERIC_UDELAY
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select HAVE_MONOTONIC_TIMER
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select RISCV_USE_ARCH_TIMER
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bool
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default n
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if SOC_UCB_RISCV
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config RISCV_ARCH
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string
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default "rv64imafd"
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config RISCV_ABI
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string
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default "lp64d"
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config RISCV_CODEMODEL
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string
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default "medany"
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endif
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