19a1bad425
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iab3549b5c4e7d845ddd284a0df3fb448e11fbdcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/53899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
43 lines
946 B
C
43 lines
946 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/mmio.h>
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#include <soc/gpio.h>
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#include <soc/spi.h>
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#include "gpio.h"
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struct pad_func {
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u8 pin_id;
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u8 func;
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};
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#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func}
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static void nor_set_gpio_pinmux(void)
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{
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const struct pad_func *ptr = NULL;
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/* GPIO 140 ~ 143 */
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struct pad_func nor_pinmux[] = {
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PAD_FUNC(SPIM2_CSB, SPINOR_CS),
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PAD_FUNC(SPIM2_CLK, SPINOR_CK),
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PAD_FUNC(SPIM2_MO, SPINOR_IO0),
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PAD_FUNC(SPIM2_MI, SPINOR_IO1),
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};
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ptr = nor_pinmux;
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for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) {
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gpio_set_pull((gpio_t){.id = ptr[i].pin_id},
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GPIO_PULL_ENABLE, GPIO_PULL_UP);
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gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
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}
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}
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void bootblock_mainboard_init(void)
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{
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mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
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nor_set_gpio_pinmux();
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setup_chromeos_gpios();
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}
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