19f5ba81be
Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29103 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
222 lines
9.8 KiB
C
222 lines
9.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/**
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* @file
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*
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* AMD User options selection for a Sabine/Lynx platform solution system
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*
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* This file is placed in the user's platform directory and contains the
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* build option selections desired for that platform.
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*
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* For Information about this file, see @ref platforminstall.
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*
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*/
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#include <stdlib.h>
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#include <AGESA.h>
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/* Select the CPU family. */
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#define INSTALL_FAMILY_10_SUPPORT FALSE
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#define INSTALL_FAMILY_12_SUPPORT TRUE
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#define INSTALL_FAMILY_14_SUPPORT FALSE
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#define INSTALL_FAMILY_15_SUPPORT FALSE
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/* Select the CPU socket type. */
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#define INSTALL_G34_SOCKET_SUPPORT FALSE
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#define INSTALL_C32_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
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#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
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#define INSTALL_FS1_SOCKET_SUPPORT TRUE
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#define INSTALL_FM1_SOCKET_SUPPORT FALSE
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#define INSTALL_FP1_SOCKET_SUPPORT TRUE
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#define INSTALL_FT1_SOCKET_SUPPORT FALSE
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#define INSTALL_AM3_SOCKET_SUPPORT FALSE
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/*
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* Agesa optional capabilities selection.
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* Uncomment and mark FALSE those features you wish to include in the build.
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* Comment out or mark TRUE those features you want to REMOVE from the build.
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*/
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#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
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#define BLDOPT_REMOVE_RDIMMS_SUPPORT FALSE
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#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
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#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
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#define BLDOPT_REMOVE_DCT_INTERLEAVE FALSE
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#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
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#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
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#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
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#define BLDOPT_REMOVE_DDR2_SUPPORT TRUE
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#define BLDOPT_REMOVE_DDR3_SUPPORT FALSE
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#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
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#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
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#define BLDOPT_REMOVE_SRAT TRUE
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#define BLDOPT_REMOVE_SLIT TRUE
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#define BLDOPT_REMOVE_WHEA TRUE
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#define BLDOPT_REMOVE_DMI FALSE
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#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
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#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
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//For revision C single-link processors
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#define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE
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/*****************************************************************************
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* Define the RELEASE VERSION string
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*
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* The Release Version string should identify the next planned release.
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* When a branch is made in preparation for a release, the release manager
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* should change/confirm that the branch version of this file contains the
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* string matching the desired version for the release. The trunk version of
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* the file should always contain a trailing 'X'. This will make sure that a
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* development build from trunk will not be confused for a released version.
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* The release manager will need to remove the trailing 'X' and update the
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* version string as appropriate for the release. The trunk copy of this file
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* should also be updated/incremented for the next expected version, + trailing 'X'
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****************************************************************************/
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// This is the delivery package title, "LlanoPI "
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// This string MUST be exactly 8 characters long
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#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
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// This is the release version number of the AGESA component
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// This string MUST be exactly 12 characters long
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#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
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/* The following definitions specify the default values for various parameters
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* in which there are no clearly defined defaults to be used in the common file.
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* The values below are based on product and BKDG content, please consult the
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* AGESA Memory team for consultation.
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*/
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#define DFLT_SCRUB_DRAM_RATE (0)
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#define DFLT_SCRUB_L2_RATE (0)
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#define DFLT_SCRUB_L3_RATE (0)
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#define DFLT_SCRUB_IC_RATE (0)
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#define DFLT_SCRUB_DC_RATE (0)
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#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
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#define DFLT_VRM_SLEW_RATE (5000)
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/* Build configuration values here.
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*/
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#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000
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#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0
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#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
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#define BLDCFG_PLAT_NUM_IO_APICS 3
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#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
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#define BLDCFG_MEM_INIT_PSTATE 0
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY
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#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
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#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
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#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
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#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
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#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
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#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
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#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
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#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
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#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
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#define BLDCFG_MEMORY_POWER_DOWN TRUE
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#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
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#define BLDCFG_ONLINE_SPARE FALSE
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#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
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#define BLDCFG_BANK_SWIZZLE TRUE
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#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
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#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
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#define BLDCFG_DQS_TRAINING_CONTROL TRUE
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#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
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#define BLDCFG_USE_BURST_MODE FALSE
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#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
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#define BLDCFG_ENABLE_ECC_FEATURE TRUE
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#define BLDCFG_ECC_REDIRECTION FALSE
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#define BLDCFG_SCRUB_DRAM_RATE 0
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#define BLDCFG_SCRUB_L2_RATE 0
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#define BLDCFG_SCRUB_L3_RATE 0
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#define BLDCFG_SCRUB_IC_RATE 0
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#define BLDCFG_SCRUB_DC_RATE 0
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#define BLDCFG_ECC_SYNC_FLOOD FALSE
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#define BLDCFG_ECC_SYMBOL_SIZE 4
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#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
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#define BLDCFG_1GB_ALIGN FALSE
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#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
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//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
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//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
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//enable HW C1E
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#define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware
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//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415
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#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6
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//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
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#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
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//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
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#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero.
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//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero.
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//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario
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//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario
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//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
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#define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE
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#define BLDCFG_STEREO_3D_PINOUT TRUE
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/* Process the options...
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* This file include MUST occur AFTER the user option selection settings
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*/
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CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
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{
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{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
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{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull },
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{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull },
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{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull },
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{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull },
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{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull },
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{ CPU_LIST_TERMINAL }
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};
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#define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList
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//#define OPTION_NB_LCLK_DPM_INIT FALSE
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//#define OPTION_POWER_GATE FALSE
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//#define OPTION_PCIE_POWER_GATE FALSE
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//#define OPTION_ALIB FALSE
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//#define OPTION_PCIe_MID_INIT FALSE
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//#define OPTION_NB_MID_INIT FALSE
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#include "cpuRegisters.h"
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#include "cpuFamRegisters.h"
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#include "cpuFamilyTranslation.h"
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#include "AdvancedApi.h"
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#include "heapManager.h"
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#include "CreateStruct.h"
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#include "cpuFeatures.h"
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#include "Table.h"
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#include "cpuEarlyInit.h"
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#include "cpuLateInit.h"
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#include "GnbInterface.h"
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#include <PlatformInstall.h>
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