19f5ba81be
Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29103 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
93 lines
2.9 KiB
C
93 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <AGESA.h>
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#include <amdlib.h>
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include <SB800.h>
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#include <stdlib.h>
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset },
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{AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
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{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/* Call the host environment interface to provide a user hook opportunity. */
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static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
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// Make sure the right speed settings are selected.
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((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
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return AGESA_SUCCESS;
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}
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/* PCIE slot reset control */
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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UINTN FcnData;
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PCIe_SLOT_RESET_INFO *ResetInfo;
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UINT32 GpioMmioAddr;
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UINT32 AcpiMmioAddr;
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UINT8 Data8;
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UINT16 Data16;
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FcnData = Data;
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ResetInfo = ConfigPtr;
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// Get SB800 MMIO Base (AcpiMmioAddr)
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WriteIo8(0xCD6, 0x27);
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Data8 = ReadIo8(0xCD7);
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Data16=Data8<<8;
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WriteIo8(0xCD6, 0x26);
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Data8 = ReadIo8(0xCD7);
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Data16|=Data8;
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AcpiMmioAddr = (UINT32)Data16 << 16;
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Status = AGESA_UNSUPPORTED;
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GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
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switch (ResetInfo->ResetId)
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{
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case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
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switch (ResetInfo->ResetControl) {
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case AssertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
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Data8 &= ~(UINT8)BIT6;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
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Status = AGESA_SUCCESS;
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break;
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case DeassertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
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Data8 |= BIT6;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
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Status = AGESA_SUCCESS;
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break;
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}
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break;
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}
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return Status;
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}
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