38ddbfb325
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
133 lines
3.2 KiB
C
133 lines
3.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <string.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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static void write_mtrr(u8 **p_nvram_pos, unsigned int idx)
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{
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msr_t msr_data;
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msr_data = rdmsr(idx);
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memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data));
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*p_nvram_pos += sizeof(msr_data);
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}
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void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
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{
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u8 *nvram_pos = mtrr_store;
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msr_t msr_data;
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u32 i;
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr_data = rdmsr(SYSCFG_MSR);
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msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr_data);
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/* Fixed MTRRs */
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write_mtrr(&nvram_pos, MTRR_FIX_64K_00000);
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write_mtrr(&nvram_pos, MTRR_FIX_16K_80000);
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write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000);
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for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_F8000; i++)
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write_mtrr(&nvram_pos, i);
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/* Disable access to AMD RdDram and WrDram extension bits */
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msr_data = rdmsr(SYSCFG_MSR);
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msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr_data);
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/* Variable MTRRs */
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for (i = MTRR_PHYS_BASE(0); i < MTRR_PHYS_BASE(8); i++)
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write_mtrr(&nvram_pos, i);
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/* SYSCFG_MSR */
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write_mtrr(&nvram_pos, SYSCFG_MSR);
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/* TOM */
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write_mtrr(&nvram_pos, TOP_MEM);
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/* TOM2 */
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write_mtrr(&nvram_pos, TOP_MEM2);
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*mtrr_store_size = nvram_pos - (u8*) mtrr_store;
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}
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void restore_mtrr(void)
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{
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volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage();
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u32 msr;
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msr_t msr_data;
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if (!msrPtr)
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return;
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disable_cache();
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr_data = rdmsr(SYSCFG_MSR);
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msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr_data);
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/* Now restore the Fixed MTRRs */
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msr_data.lo = *msrPtr;
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msrPtr ++;
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msr_data.hi = *msrPtr;
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msrPtr ++;
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wrmsr(MTRR_FIX_64K_00000, msr_data);
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msr_data.lo = *msrPtr;
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msrPtr ++;
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msr_data.hi = *msrPtr;
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msrPtr ++;
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wrmsr(MTRR_FIX_16K_80000, msr_data);
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msr_data.lo = *msrPtr;
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msrPtr ++;
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msr_data.hi = *msrPtr;
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msrPtr ++;
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wrmsr(MTRR_FIX_16K_A0000, msr_data);
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for (msr = MTRR_FIX_4K_C0000; msr <= MTRR_FIX_4K_F8000; msr++) {
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msr_data.lo = *msrPtr;
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msrPtr ++;
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msr_data.hi = *msrPtr;
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msrPtr ++;
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wrmsr(msr, msr_data);
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}
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/* Disable access to AMD RdDram and WrDram extension bits */
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msr_data = rdmsr(SYSCFG_MSR);
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msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr_data);
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/* Restore the Variable MTRRs */
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for (msr = MTRR_PHYS_BASE(0); msr <= MTRR_PHYS_MASK(7); msr++) {
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msr_data.lo = *msrPtr;
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msrPtr ++;
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msr_data.hi = *msrPtr;
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msrPtr ++;
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wrmsr(msr, msr_data);
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}
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/* Restore SYSCFG MTRR */
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msr_data.lo = *msrPtr;
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msrPtr ++;
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msr_data.hi = *msrPtr;
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msrPtr ++;
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wrmsr(SYSCFG_MSR, msr_data);
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}
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