1b410d9ab9
It's not the AGESA code that generates most of the ACPI tables, so rename the function. This also aligns the other SoCs more with Genoa. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b2e6c4cb7139c8bde01b4440ab2e923a1086827 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80217 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Update for Glinda */
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#include <amdblocks/data_fabric.h>
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#include <amdblocks/fsp.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include <types.h>
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#include "chip.h"
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static const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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};
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struct device_operations glinda_pci_domain_ops = {
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.read_resources = amd_pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = amd_pci_domain_scan_bus,
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.acpi_name = soc_acpi_name,
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.acpi_fill_ssdt = amd_pci_domain_fill_ssdt,
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};
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static void soc_init(void *chip_info)
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{
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default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
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amd_fsp_silicon_init();
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data_fabric_set_mmio_np();
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fch_init(chip_info);
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}
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static void soc_final(void *chip_info)
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{
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fch_final(chip_info);
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}
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struct chip_operations soc_amd_glinda_ops = {
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CHIP_NAME("AMD Glinda SoC")
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.init = soc_init,
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.final = soc_final
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};
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