1c2f49e74a
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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#include "cs5536.h"
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static void southbridge_init(struct device *dev)
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{
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printk_err("cs5536: %s\n", __FUNCTION__);
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setup_i8259();
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}
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static void southbridge_enable(struct device *dev)
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{
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struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
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msr_t msr;
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struct device *gpiodev;
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unsigned short gpiobase = MDD_GPIO;
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printk_err("%s: dev is %p\n", __FUNCTION__, dev);
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if (chip_info->lpc_serirq_enable) {
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msr.lo = chip_info->lpc_serirq_enable;
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msr.hi = 0;
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wrmsr(MDD_LPC_SIRQ, msr);
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}
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if (chip_info->lpc_irq) {
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msr.lo = chip_info->lpc_irq;
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msr.hi = 0;
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wrmsr(MDD_IRQM_LPC, msr);
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}
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if (chip_info->enable_gpio0_inta){
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rdmsr(MDD_IRQM_ZHIGH, msr);
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msr.lo |= 0x10;
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wrmsr(MDD_IRQM_ZHIGH, msr);
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/* todo: look the device up. But we know that gpiobase is 0x6100 */
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/* oh gosh, all the defines from AMD assume 6100. Don't bother looking up! */
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outl(GPIOL_0_SET|GPIOL_1_SET|GPIOL_3_SET, GPIOL_INPUT_ENABLE);
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outl(GPIOL_0_SET,GPIOL_EVENTS_ENABLE);
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/* magic stuff */
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outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
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outl(GPIOL_0_SET, GPIO_MAPPER_X);
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}
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}
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static void cs5536_pci_dev_enable_resources(device_t dev)
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{
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printk_err("cs5536.c: %s()\n", __FUNCTION__);
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pci_dev_enable_resources(dev);
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enable_childrens_resources(dev);
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}
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static struct device_operations southbridge_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = cs5536_pci_dev_enable_resources,
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.init = southbridge_init,
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.enable = southbridge_enable,
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.scan_bus = scan_static_bus,
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};
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static struct pci_driver cs5536_pci_driver __pci_driver = {
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.ops = &southbridge_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_CS5536_ISA
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};
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