1c6d8a9cf4
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
133 lines
3.0 KiB
C
133 lines
3.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootstate.h>
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#include <cpu/amd/mtrr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <romstage_handoff.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include "chip.h"
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/* Supplied by i2c.c */
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extern struct device_operations picasso_i2c_mmio_ops;
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extern const char *i2c_acpi_name(const struct device *dev);
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struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = picasso_init_cpus,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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};
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const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type == DEVICE_PATH_USB) {
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switch (dev->path.usb.port_type) {
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case 0:
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/* Root Hub */
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return "RHUB";
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case 3:
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/* USB3 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "SS01";
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case 1: return "SS02";
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case 2: return "SS03";
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}
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break;
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}
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return NULL;
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}
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case GFX_DEVFN:
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return "IGFX";
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case PCIE0_DEVFN:
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return "PBR4";
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case PCIE1_DEVFN:
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return "PBR5";
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case PCIE2_DEVFN:
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return "PBR6";
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case PCIE3_DEVFN:
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return "PBR7";
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case PCIE4_DEVFN:
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return "PBR8";
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case HDA1_DEVFN:
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return "AZHD";
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case LPC_DEVFN:
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return "LPCB";
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case SATA_DEVFN:
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return "STCR";
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case SMBUS_DEVFN:
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return "SBUS";
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case XHCI0_DEVFN:
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return "XHC0";
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case XHCI1_DEVFN:
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return "XHC1";
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default:
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return NULL;
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}
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};
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struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.acpi_name = soc_acpi_name,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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dev->ops = &pci_domain_ops;
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &cpu_bus_ops;
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else if (dev->path.type == DEVICE_PATH_PCI)
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sb_enable(dev);
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else if (dev->path.type == DEVICE_PATH_MMIO)
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if (i2c_acpi_name(dev) != NULL)
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dev->ops = &picasso_i2c_mmio_ops;
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}
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static void soc_init(void *chip_info)
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{
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southbridge_init(chip_info);
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setup_bsp_ramtop();
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}
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static void soc_final(void *chip_info)
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{
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southbridge_final(chip_info);
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}
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struct chip_operations soc_amd_picasso_ops = {
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CHIP_NAME("AMD Picasso SOC")
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.enable_dev = enable_dev,
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.init = soc_init,
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.final = soc_final
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};
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