1c6d8a9cf4
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
88 lines
2.6 KiB
Makefile
88 lines
2.6 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-y += bootblock/esram_init.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += i2c.c
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bootblock-y += reg_access.c
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bootblock-y += tsc_freq.c
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bootblock-y += uart_common.c
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verstage-y += i2c.c
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verstage-y += reg_access.c
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verstage-y += tsc_freq.c
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verstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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romstage-y += i2c.c
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romstage-y += memmap.c
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romstage-y += reg_access.c
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romstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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romstage-y += tsc_freq.c
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romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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romstage-y += reset.c
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postcar-y += fsp_params.c
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postcar-y += i2c.c
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postcar-y += reg_access.c
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postcar-y += tsc_freq.c
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postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += ehci.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio_i2c.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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ramstage-y += northcluster.c
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ramstage-y += reg_access.c
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ramstage-y += reset.c
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ramstage-y += sd.c
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ramstage-y += spi.c
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ramstage-y += spi_debug.c
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ramstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/quark
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CPPFLAGS_common += -I$(src)/soc/intel/quark/include
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CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp
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# Chipset microcode path
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CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
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# Since FSP-M runs in CAR we need to relocate it to a specific address
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$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_ESRAM_LOC)
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# Add the FSP binary to the CBFS image
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cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
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fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
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fsp.bin-position := $(CONFIG_FSP_LOC)
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fsp.bin-type := raw
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# Add the chipset microcode file to the CBFS image
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cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
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rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
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rmu.bin-position := $(CONFIG_RMU_LOC)
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rmu.bin-type := raw
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endif # CONFIG_SOC_INTEL_QUARK
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