1cae45432e
Also change some of the types to match the register widths of the controller. It is expected that these prototypes will be used with SMBus host controllers inside AMD chipsets as well, thus the change of location. Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
51 lines
1.4 KiB
C
51 lines
1.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2019 3mdeb
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* Copyright (C) 2019 Eltan B.V.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <device/pci_def.h>
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#include <device/pci_type.h>
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#include <device/pci_ops.h>
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#include <device/smbus_host.h>
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#include <soc/smbus.h>
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int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
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{
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
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#else
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struct device *dev = pcidev_on_root(SMBUS_DEV, SMBUS_FUNC);
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#endif
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u32 smbase;
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u32 smb_ctrl_reg;
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int status;
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/* SMBus I/O BAR */
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smbase = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE;
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/* Enable I2C_EN bit in HOSTC register */
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smb_ctrl_reg = pci_read_config32(dev, HOSTC);
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pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
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status = do_i2c_block_write(smbase, addr, bytes, buf);
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/* Restore I2C_EN bit */
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pci_write_config32(dev, HOSTC, smb_ctrl_reg);
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return status;
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}
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