1cb9cd5798
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Eric W. Biederman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef CPU_X86_CACHE
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#define CPU_X86_CACHE
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#include <cpu/x86/cr.h>
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#define CR0_CacheDisable (CR0_CD)
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#define CR0_NoWriteThrough (CR0_NW)
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#if !defined(__ASSEMBLER__)
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static inline void wbinvd(void)
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{
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asm volatile ("wbinvd" ::: "memory");
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}
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static inline void invd(void)
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{
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asm volatile("invd" ::: "memory");
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}
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static inline void clflush(void *addr)
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{
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asm volatile ("clflush (%0)"::"r" (addr));
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}
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/* The following functions require the __always_inline due to AMD
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* function STOP_CAR_AND_CPU that disables cache as
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* RAM, the cache as RAM stack can no longer be used. Called
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* functions must be inlined to avoid stack usage. Also, the
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* compiler must keep local variables register based and not
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* allocated them from the stack. With gcc 4.5.0, some functions
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* declared as inline are not being inlined. This patch forces
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* these functions to always be inlined by adding the qualifier
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* __always_inline to their declaration.
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*/
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static __always_inline void enable_cache(void)
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{
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CRx_TYPE cr0;
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cr0 = read_cr0();
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cr0 &= ~(CR0_CD | CR0_NW);
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write_cr0(cr0);
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}
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static __always_inline void disable_cache(void)
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{
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/* Disable and write back the cache */
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CRx_TYPE cr0;
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cr0 = read_cr0();
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cr0 |= CR0_CD;
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wbinvd();
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write_cr0(cr0);
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wbinvd();
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}
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void x86_enable_cache(void);
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#endif /* !__ASSEMBLER__ */
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#endif /* CPU_X86_CACHE */
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