1ce416eda1
Previously incorrect sets of SATA ports were enabled. There are no publically available schematics, but I am almost certain the new values are correct. The original 0x33 value was carlessly copy pasted, and only enables ports 0, 1, 4, 5, leaving 2, 3 disabled. On the SFF, with 0x33 only the first 2 ports worked. I have verified by plugging in devices under the stock firmware that 0, 1, 2 are the ones that should be enabled, so setting the value to 0x7 per datasheet. This was also tested in practice to work. I don't have an MT, but I was told the two white ports didn't work with 0x33, so those are most certainly ports 3, 4, hence me setting the value to 0xf. If the MT's working ports are port 0, 1 on the PCH this is correct. Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
81 lines
2.3 KiB
Plaintext
81 lines
2.3 KiB
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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chip northbridge/intel/haswell
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# This mainboard has VGA
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register "gpu_ddi_e_connected" = "1"
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chip cpu/intel/haswell
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device cpu_cluster 0 on ops haswell_cpu_bus_ops end
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end
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device domain 0 on
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ops haswell_pci_domain_ops
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subsystemid 0x1028 0x05a5 inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe graphics
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device pci 02.0 on end # VGA controller
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device pci 03.0 on end # Mini-HD audio
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chip southbridge/intel/lynxpoint
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register "gen1_dec" = "0x007c0a01"
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register "gen2_dec" = "0x007c0901"
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register "gen3_dec" = "0x003c07e1"
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register "gen4_dec" = "0x001c0901"
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register "sata_port_map" = "0x7"
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device pci 14.0 on end # xHCI controller
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device pci 16.0 on end # Management Engine interface 1
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device pci 16.1 off end # Management Engine interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 on end # Management Engine KT
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device pci 19.0 on # Intel Gigabit Ethernet
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subsystemid 0x1028 0x05a4
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end
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device pci 1a.0 on end # EHCI controller #2
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device pci 1b.0 on end # HD audio controller
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device pci 1c.0 off end
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device pci 1c.1 off end
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device pci 1c.2 off end
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device pci 1c.3 off end
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device pci 1c.4 on end # PCIe 4x slot
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device pci 1c.5 off end
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device pci 1c.6 off end
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device pci 1c.7 off end
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device pci 1d.0 on end # EHCI controller #1
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device pci 1f.0 on # LPC bridge
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chip superio/smsc/sch555x
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device pnp 2e.0 on # EMI
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io 0x60 = 0xa00
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end
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device pnp 2e.1 on # 8042
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io 0x60 = 0x60
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irq 0x0f = 0
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.7 on # UART1
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io 0x60 = 0x3f8
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irq 0x0f = 2
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irq 0x70 = 4
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end
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device pnp 2e.8 off end # UART2
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device pnp 2e.c on # LPC interface
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io 0x60 = 0x2e
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end
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device pnp 2e.a on # Runtime registers
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io 0x60 = 0xa40
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end
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device pnp 2e.b off end # Floppy Controller
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device pnp 2e.11 off end # Parallel Port
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end
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end
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device pci 1f.2 on end # SATA controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA controller 2
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device pci 1f.6 off end # Thermal
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end
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end
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end
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