system76-coreboot

Files

Xavi Drudis Ferran 1d80e51017 Prepare for next patches (Improving BKDG implementation of P-states,

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj],
Northbridge/core synchronization FIFO pointer adjust, to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2011-02-27 23:50:30 +00:00

apic_timer.c

Split the two usages of __ROMCC__:

2009-11-06 17:02:51 +00:00

defaults.h

Clear bit 35 of msr c001_102a in Fam10 rev C cores.

2010-09-17 00:13:52 +00:00

fidvid.c

Prepare for next patches (Improving BKDG implementation of P-states,

2011-02-27 23:50:30 +00:00

init_cpus.c

Make AMD Fam10h CPU microcode updates optional in Expert mode