1e1b866d28
Replace the use of the old device_t definition inside southbridge/amd/cimx. Change-Id: Ibe2766b956b0ca02be63621aee9a230b16d9923b Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include "Platform.h"
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#include "sb_cimx.h"
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#include "sb700_cfg.h" /*sb700_cimx_config*/
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include "smbus.h"
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/**
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* @brief Get SouthBridge device number
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* @param[in] bus target bus number
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* @return southbridge device number
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*/
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u32 get_sbdn(u32 bus)
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{
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pci_devfn_t dev;
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printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__);
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dev = pci_locate_device_on_bus(
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PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM),
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bus);
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printk(BIOS_SPEW, "SB700 - Early.c - %s - End.\n", __func__);
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return (dev >> 15) & 0x1f;
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}
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/**
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* @brief Enable A-Link Express Configuration DMA Access.
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*/
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/**
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* @brief South Bridge CIMx romstage entry,
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* wrapper of sbPowerOnInit entry point.
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*/
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void sb_Poweron_Init(void)
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{
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AMDSBCFG sb_early_cfg;
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printk(BIOS_SPEW, "cimx/sb700 early.c, %s() Start:\n", __func__);
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/* Enable A-Link Base Address */
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//sb_enable_alink ();
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sb700_cimx_config(&sb_early_cfg);
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sbPowerOnInit(&sb_early_cfg);
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printk(BIOS_SPEW, "cimx/sb700 early.c, %s() End\n", __func__);
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}
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void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
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{
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/* TODO: Now assume wio_index=0 */
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pci_devfn_t dev;
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u8 reg8;
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//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
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dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */
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pci_write_config32(dev, 0x64, base);
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reg8 = pci_read_config8(dev, 0x48);
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reg8 |= 1 << 2;
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pci_write_config8(dev, 0x48, reg8);
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}
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void sb7xx_51xx_disable_wideio(u8 wio_index)
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{
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/* TODO: Now assume wio_index=0 */
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pci_devfn_t dev;
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u8 reg8;
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//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
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dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */
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pci_write_config32(dev, 0x64, 0);
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reg8 = pci_read_config8(dev, 0x48);
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reg8 &= ~(1 << 2);
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pci_write_config8(dev, 0x48, reg8);
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}
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