1e67adbc73
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
125 lines
2.7 KiB
C
125 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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#include <amdblocks/i2c.h>
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#include <amdblocks/post_codes.h>
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#include "chip.h"
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const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type == DEVICE_PATH_USB) {
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switch (dev->path.usb.port_type) {
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case 0:
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/* Root Hub */
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return "RHUB";
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case 2:
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/* USB2 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "HS01";
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case 1: return "HS02";
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case 2: return "HS03";
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case 3: return "HS04";
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case 4: return "HS05";
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case 5: return "HS06";
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case 6: return "HS07";
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case 7: return "HS08";
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}
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break;
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case 3:
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/* USB3 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "SS01";
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case 1: return "SS02";
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case 2: return "SS03";
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}
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break;
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}
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return NULL;
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}
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case GFX_DEVFN:
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return "IGFX";
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case PCIE0_DEVFN:
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return "PBR4";
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case PCIE1_DEVFN:
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return "PBR5";
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case PCIE2_DEVFN:
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return "PBR6";
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case PCIE3_DEVFN:
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return "PBR7";
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case PCIE4_DEVFN:
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return "PBR8";
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case EHCI1_DEVFN:
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return "EHC0";
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case SD_DEVFN:
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return "SDCN";
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case XHCI_DEVFN:
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return "XHC0";
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default:
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return NULL;
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}
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};
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struct device_operations stoneyridge_pci_domain_ops = {
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.read_resources = domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = domain_enable_resources,
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.scan_bus = pci_domain_scan_bus,
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.acpi_name = soc_acpi_name,
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};
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static void soc_init(void *chip_info)
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{
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fch_init(chip_info);
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}
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static void soc_final(void *chip_info)
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{
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fch_final(chip_info);
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fam15_finalize(chip_info);
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}
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struct chip_operations soc_amd_stoneyridge_ops = {
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CHIP_NAME("AMD StoneyRidge SOC")
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.init = soc_init,
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.final = soc_final
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};
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static void earliest_ramstage(void *unused)
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{
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if (!acpi_is_wakeup_s3()) {
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post_code(POSTCODE_PSP_LOAD_SMU);
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if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
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psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
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post_code(POSTCODE_AGESA_AMDINITENV);
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do_agesawrapper(AMD_INIT_ENV, "amdinitenv");
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} else {
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/* Complete the initial system restoration */
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post_code(POSTCODE_AGESA_AMDS3LATERESTORE);
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do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore");
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL);
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