1e78165cdc
Instead of having a magic entry in the CPU device ID table list to tell find_cpu_driver that it has reached the end of the list, introduce and use CPU_TABLE_END. Since the vendor entry in the CPU device ID struct is compared against X86_VENDOR_INVALID which is 0, use X86_VENDOR_INVALID instead of the 0 in the CPU_TABLE_END definition. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I0cae6d65b2265cf5ebf90fe1a9d885d0c489eb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
|
|
#include <acpi/acpi.h>
|
|
#include <amdblocks/cpu.h>
|
|
#include <amdblocks/iomap.h>
|
|
#include <amdblocks/mca.h>
|
|
#include <console/console.h>
|
|
#include <cpu/amd/microcode.h>
|
|
#include <cpu/cpu.h>
|
|
#include <cpu/x86/mp.h>
|
|
#include <cpu/x86/mtrr.h>
|
|
#include <device/device.h>
|
|
#include <soc/cpu.h>
|
|
#include <soc/iomap.h>
|
|
|
|
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
|
|
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
|
|
|
|
/* MP and SMM loading initialization. */
|
|
|
|
void mp_init_cpus(struct bus *cpu_bus)
|
|
{
|
|
extern const struct mp_ops amd_mp_ops_with_smm;
|
|
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
|
|
die_with_post_code(POST_HW_INIT_FAILURE,
|
|
"mp_init_with_smm failed. Halting.\n");
|
|
|
|
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
|
|
mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
|
|
FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
|
|
|
|
/* SMMINFO only needs to be set up when booting from S5 */
|
|
if (!acpi_is_wakeup_s3())
|
|
apm_control(APM_CNT_SMMINFO);
|
|
|
|
}
|
|
|
|
static void model_17_init(struct device *dev)
|
|
{
|
|
check_mca();
|
|
set_cstate_io_addr();
|
|
|
|
amd_update_microcode_from_cbfs();
|
|
}
|
|
|
|
static struct device_operations cpu_dev_ops = {
|
|
.init = model_17_init,
|
|
};
|
|
|
|
static struct cpu_device_id cpu_table[] = {
|
|
{ X86_VENDOR_AMD, RAVEN1_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
|
|
{ X86_VENDOR_AMD, PICASSO_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
|
|
{ X86_VENDOR_AMD, RAVEN2_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
|
|
CPU_TABLE_END
|
|
};
|
|
|
|
static const struct cpu_driver model_17 __cpu_driver = {
|
|
.ops = &cpu_dev_ops,
|
|
.id_table = cpu_table,
|
|
};
|