1efe2578c0
This patch changes the mapping of SRAM from non-secure to secure. Without this patch, mmu_config_range() can not work when MMU is enabled. The new config is still in non-secure cache since TTB section is allocated in SRAM which is mapped as non-secure. BUG=b:80501386 TEST=Boots correctly on Kukui and Elm Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <arch/mmu.h>
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#include <symbols.h>
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#include <soc/symbols.h>
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#include <soc/infracfg.h>
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#include <soc/mcucfg.h>
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#include <soc/mmu_operations.h>
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void mtk_soc_after_dram(void)
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{
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mmu_config_range(_dram_dma, _dram_dma_size, NONSECURE_UNCACHED_MEM);
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mtk_mmu_disable_l2c_sram();
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}
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void mtk_soc_disable_l2c_sram(void)
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{
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/* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max
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* available L2 cache for A53 in MT8173. */
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write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8);
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/* turn off the l2c sram clock */
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write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN);
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}
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