1f9c07fcd7
This patch binds PCIe lanes 2 and 3 to one PCIe device. PCIe device 2.4 becomes x2. Tested with the connected FPGA on PCIe 2.4. FPGA doubles transfer rate from/to the AMD. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Icee567272312a7df4c3b5a6db5b420a054ec3230 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15905 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
113 lines
3.9 KiB
Plaintext
113 lines
3.9 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2013 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/amd/agesa/family16kb/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family16kb
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device lapic 0 on end
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end
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end
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device domain 0 on
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subsystemid 0x1022 0x1410 inherit
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chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
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chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9835
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device pci 1.1 on end # Internal Multimedia
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device pci 2.0 on end # PCIe Host Bridge
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device pci 2.1 on end # x4 PCIe Slot
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device pci 2.2 on end # PCIe Q7 Realtek GBit LAN
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device pci 2.3 on end # PCIe CB Realtek GBit LAN
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device pci 2.4 on end # x2 PCIe Microsemi FPGA
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end #chip northbridge/amd/agesa/family16kb
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chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
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device pci 10.0 on end # XHCI HC0
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.2 on end # USB
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device pci 13.0 on end # USB
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device pci 13.2 on end # USB
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device pci 14.0 on end # SM
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on # LPC 0x439d
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chip superio/fintek/f81866d
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register "hwm_amd_tsi_addr" = "0x98" # Set to AMD
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register "hwm_amd_tsi_control" = "0x02" # Set to AMD
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register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM
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register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode
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register "hwm_fan3_control" = "0x00" # Fan control 23kHz
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register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz
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register "hwm_fan2_bound1" = "0x3C" # 60°C
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register "hwm_fan2_bound2" = "0x32" # 50°C
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register "hwm_fan2_bound3" = "0x28" # 40°C
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register "hwm_fan2_bound4" = "0x1E" # 30°C
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register "hwm_fan2_seg1_speed" = "0xFF" # 100%
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register "hwm_fan2_seg2_speed" = "0xD9" # 85%
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register "hwm_fan2_seg3_speed" = "0xB2" # 70%
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register "hwm_fan2_seg4_speed" = "0x99" # 60%
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register "hwm_fan2_seg5_speed" = "0x80" # 50%
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register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor
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device pnp 4e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.3 off end # Parallel Port
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device pnp 4e.4 on # Hardware Monitor
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io 0x60 = 0x295
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irq 0x70 = 0
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end
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device pnp 4e.5 off # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 4e.6 off end # GPIO
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device pnp 4e.7 on end # WDT
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device pnp 4e.a off end # PME
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device pnp 4e.10 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.11 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 4e.12 off # COM3
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end
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device pnp 4e.13 off # COM4
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end
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device pnp 4e.14 off # COM5
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end
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device pnp 4e.15 off # COM6
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end
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end # f81866d
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end #LPC
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device pci 14.7 on end # SD
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end #chip southbridge/amd/hudson
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
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end #domain
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end #northbridge/amd/agesa/family16kb/root_complex
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