9029265cf5
Well, it turned out to be more as some gaps ;) but we finally have xHCI running. It's well tested against a QM77 Ivy Bridge board. We have no SuperSpeed support (yet). On Ivy Bridge, SuperSpeed is not advertised and USB 3 devices will just work at HighSpeed. There are still some bit fields in xhci_private.h, so this might need little more work to run on ARM. Change-Id: I7a2cb3f226d24573659142565db38b13acdc218c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3452 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
140 lines
4.3 KiB
C
140 lines
4.3 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2013 secunet Security Networks AG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define USB_DEBUG
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#include <usb/usb.h>
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#include "generic_hub.h"
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#include "xhci_private.h"
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#include "xhci.h"
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static int
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xhci_rh_hub_status_changed(usbdev_t *const dev)
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{
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xhci_t *const xhci = XHCI_INST(dev->controller);
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const int changed = !!(xhci->opreg->usbsts & USBSTS_PCD);
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if (changed)
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xhci->opreg->usbsts =
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(xhci->opreg->usbsts & USBSTS_PRSRV_MASK) | USBSTS_PCD;
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return changed;
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}
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static int
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xhci_rh_port_status_changed(usbdev_t *const dev, const int port)
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{
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xhci_t *const xhci = XHCI_INST(dev->controller);
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volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
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const int changed = !!(*portsc & PORTSC_CSC);
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/* always clear all the status change bits */
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*portsc = (*portsc & PORTSC_RW_MASK) | 0x00ef0000;
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return changed;
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}
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static int
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xhci_rh_port_connected(usbdev_t *const dev, const int port)
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{
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xhci_t *const xhci = XHCI_INST(dev->controller);
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volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
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return *portsc & PORTSC_CCS;
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}
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static int
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xhci_rh_port_in_reset(usbdev_t *const dev, const int port)
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{
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xhci_t *const xhci = XHCI_INST(dev->controller);
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volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
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return !!(*portsc & PORTSC_PR);
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}
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static int
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xhci_rh_port_enabled(usbdev_t *const dev, const int port)
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{
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xhci_t *const xhci = XHCI_INST(dev->controller);
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volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
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return !!(*portsc & PORTSC_PED);
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}
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static int
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xhci_rh_port_speed(usbdev_t *const dev, const int port)
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{
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xhci_t *const xhci = XHCI_INST(dev->controller);
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volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
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if (*portsc & PORTSC_PED) {
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return ((*portsc & PORTSC_PORT_SPEED_MASK)
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>> PORTSC_PORT_SPEED_START)
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- 1;
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} else {
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return -1;
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}
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}
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static int
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xhci_rh_start_port_reset(usbdev_t *const dev, const int port)
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{
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xhci_t *const xhci = XHCI_INST(dev->controller);
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volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
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*portsc = (*portsc & PORTSC_RW_MASK) | PORTSC_PR;
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return 0;
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}
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static const generic_hub_ops_t xhci_rh_ops = {
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.hub_status_changed = xhci_rh_hub_status_changed,
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.port_status_changed = xhci_rh_port_status_changed,
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.port_connected = xhci_rh_port_connected,
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.port_in_reset = xhci_rh_port_in_reset,
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.port_enabled = xhci_rh_port_enabled,
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.port_speed = xhci_rh_port_speed,
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.enable_port = NULL,
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.disable_port = NULL,
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.start_port_reset = xhci_rh_start_port_reset,
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.reset_port = generic_hub_rh_resetport,
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};
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void
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xhci_rh_init (usbdev_t *dev)
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{
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/* we can set them here because a root hub _really_ shouldn't
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appear elsewhere */
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dev->address = 0;
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dev->hub = -1;
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dev->port = -1;
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const int num_ports = /* TODO: maybe we need to read extended caps */
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(XHCI_INST(dev->controller)->capreg->hcsparams1 >> 24) & 0xff;
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generic_hub_init(dev, num_ports, &xhci_rh_ops);
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usb_debug("xHCI: root hub init done\n");
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}
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