1fc0edd9fe
Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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#include "i82801gx.h"
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typedef struct southbridge_intel_i82801gx_config config_t;
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static void ide_init(struct device *dev)
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{
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u16 ideTimingConfig;
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u32 reg32;
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u32 enable_primary, enable_secondary;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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printk(BIOS_DEBUG, "i82801gx_ide: initializing...");
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if (config == NULL) {
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printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
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// Trying to set somewhat safe defaults instead of bailing out.
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enable_primary = enable_secondary = 1;
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} else {
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enable_primary = config->ide_enable_primary;
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enable_secondary = config->ide_enable_secondary;
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}
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER);
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/* Native Capable, but not enabled. */
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pci_write_config8(dev, 0x09, 0x8a);
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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ideTimingConfig |= IDE_SITRE;
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if (enable_primary) {
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/* Enable primary IDE interface. */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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ideTimingConfig |= IDE_ISP_3_CLOCKS;
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ideTimingConfig |= IDE_RCT_1_CLOCKS;
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ideTimingConfig |= IDE_IE0;
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ideTimingConfig |= IDE_TIME0; // TIME0
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printk(BIOS_DEBUG, " IDE0");
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}
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pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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ideTimingConfig |= IDE_SITRE;
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if (enable_secondary) {
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/* Enable secondary IDE interface. */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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ideTimingConfig |= IDE_ISP_3_CLOCKS;
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ideTimingConfig |= IDE_RCT_1_CLOCKS;
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ideTimingConfig |= IDE_IE0;
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ideTimingConfig |= IDE_TIME0;
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printk(BIOS_DEBUG, " IDE1");
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}
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pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
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/* Set IDE I/O Configuration */
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reg32 = 0;
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/* FIXME: only set FAST_* for ata/100, only ?CBx for ata/66 */
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if (enable_primary)
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reg32 |= SIG_MODE_PRI_NORMAL | FAST_PCB0 | PCB0 | FAST_PCB1 | PCB1;
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if (enable_secondary)
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reg32 |= SIG_MODE_SEC_NORMAL | FAST_SCB0 | SCB0 | FAST_SCB1 | SCB1;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */
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printk(BIOS_DEBUG, "\n");
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.enable = i82801gx_enable,
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.ops_pci = &pci_dev_ops_pci,
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};
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/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
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static const struct pci_driver i82801gx_ide __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x27df,
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};
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