1fd7508121
With USBDEBUG selected, the file is built for both romstage and ramstage. For the ramstage build, we need to explicitly use the simple PCI config operations without devicetree. Change-Id: I2de8d9c77bb458ba797c3aac9e2cd0d653e06684 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
58 lines
1.8 KiB
C
58 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Tyan Computer
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* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
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* Copyright (C) 2006,2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <stdint.h>
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#include <arch/io.h>
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#include <usbdebug.h>
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#include <device/pci_def.h>
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#include "mcp55.h"
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void set_debug_port(unsigned int port)
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{
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u32 dword;
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device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
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/* Write the port number to 0x74[15:12]. */
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dword = pci_read_config32(dev, 0x74);
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dword &= ~(0xf << 12);
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dword |= (port << 12);
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pci_write_config32(dev, 0x74, dword);
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}
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void enable_usbdebug(unsigned int port)
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{
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device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
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/* Mark the requested physical USB port (1-15) as the Debug Port. */
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set_debug_port(port);
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/* Set the EHCI BAR address. */
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pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
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/* Enable access to the EHCI memory space registers. */
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pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
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}
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